This patchset adds virtualization support to our GICv5 model, and lets the "virt" board use -machine gic-version=x-5,virtualization=on.
Virtualization in the GICv5 is more complicated than it is in GICv3. This is because in GICv3 virtualization is mostly delegated to software, and only the CPU interface has hardware virtualization support. In GICv5 the hardware does a lot more of the work, so virtualization support is needed in both the CPU interface and the IRS. I've structured this patchset as: * initial preparatory and bug-fixing patches * add virt support to the cpu interface * add virt support to the IRS * remove the check in virt that stops the user enabling virt The first 11 patches have been on this list already; I've copied across Reviewed-by tags for those patches which got them. The current spec for the GICv5 is at https://support.arm.com/documentation/aes0070/00eac0/ The kernel support for using GICv5 virtualization is not yet in mainline, but it has landed in the kvmarm/next tree: https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git next Similarly kvmtool support to run the inner guest is still work in progress, but the tree at https://gitlab.arm.com/linux-arm/kvmtool-sb.git gicv5_wip will work with the kvmarm/next tree. This series can pass the kernel's vgic_v5 selftest, and boot an inner guest to userspace with kvmtool. In an ideal world I'd like to land this for 11.2, but I appreciate that it's a lot of code to review and only two weeks til softfreeze; we'll see how it goes. If you want a git branch of this I've pushed the patchset to https://gitlab.com/pm215/qemu.git gicv5-virt thanks -- PMM Peter Maydell (86): hw/intc/arm_gicv5: Make IRS_IDR0 reads return actual value, not 0 hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR hw/intc/arm_gicv5: Ignore low bits in L1_ISTE.L2_ADDR hw/intc/arm_gicv5: Regularize spacing in config_readl() switch hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state hw/intc/arm_gicv5: Free memory in finalize target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 hw/intc/arm_gicv5: Pass CPU index to CPU interface hw/intc/arm_gicv5: Pass cpuidx rather than iaffid in gicv5_get_hppi() hw/intc/arm_gicv5: Use correct type for value in lpi_cache_get_hppi() hw/intc/arm_gicv5: Relax QEMU_GICV5_MIN_LPI_ID_BITS to 0 target/arm: GICv5 cpuif: Implement ICH_APR_EL2 target/arm: GICv5 cpuif: Implement ICH_PPI_{ENABLE,PEND,ACTIVE} regs target/arm: GICv5 cpuif: Implement ICH_PPI_PRIORITYR<n>_EL2 target/arm: GICv5 cpuif: Implement ICH_PPI_DVIR<n>_EL2 target/arm: GICv5 cpuif: Implement ICH_VCTLR_EL2 and ICH_VCMR_EL2 target/arm: GICv5 cpuif: Implement GIC fine-grained trap registers target/arm: GICv5 cpuif: Mark GIC registers for fine-grained traps target/arm: GICv5 cpuif: Mark GIC insns for fine-grained traps target/arm: GICv5 cpuif: Implement ICC_SRE_ELx target/arm: GICv5 cpuif: Implement ICH_PPI_HVIR<n>_EL2 target/arm: GICv5 cpuif: Implement ICV_APR_EL1 target/arm: GICv5 cpuif: Implement ICV_CR0_EL1 target/arm: GICv5 cpuif: Implement ICV_PCR_EL1 target/arm: GICv5 cpuif: Implement ICV_PPI_ENABLER<n>_EL1 target/arm: GICv5 cpuif: Implement ICV_PPI_PRIORITYR<n>_EL1 target/arm: GICv5 cpuif: Add comment about ICV_PPI_HMR<n>_EL1 target/arm: GICv5 cpuif: Implement ICV_PPI_CACTIVER<n>_EL1, ICV_PPI_SACTIVER<n>_EL1 target/arm: GICv5 cpuif: Implement ICV_PPI_CPENDR<n>_EL1, ICV_PPI_SPENDR<n>_EL1 target/arm: GICv5 cpuif: Calculate current virtual PPI HPPI target/arm: GICv5 cpuif: Add virtual support to IRS/cpuif HPPI APIs target/arm: GICv5 cpuif: Implement ICV_HPPIR_EL1 target/arm: GICv5 cpuif: Implement gicv5_update_virq_vfiq() target/arm: GICv5 cpuif: Implement ICH_CONTEXTR_EL2 target/arm: GICv5 cpuif: ask the GIC for the virtual HPPI target/arm: GICv5 cpuif: Handle LD/VD insns when setting domain/virtual args target/arm: GICv5 cpuif: Handle virtual interrupts for GIC CDEOI target/arm: GICv5 cpuif: Handle virtual interrupts for GIC CDDI target/arm: GICv5 cpuif: Handle virtual interrupts for GICR CDIA, CDNMIA target/arm: GICv5 cpuif: Handle GIC VDPEND VM argument target/arm: GICv5 cpuif: Implement GIC VDnnn insns target/arm: GICv5 cpuif: Implement GIC LDnnn insns target/arm: GICv5 cpuif: Handle PPI injection in vPPI pending reads target/arm: GICv5 cpuif: Handle PPI injection in vPPI pending writes target/arm: GICv5 cpuif: Handle injected PPIs in GICR CDIA target/arm: GICv5 cpuif: Update on HCR_EL2.{NV,NV1} and SCR_EL3.NS changes target/arm: GICv5 cpuif: Update VFIQ/VIRQ when direct-injected PPIs change hw/intc: Move GICv5 register and data definitions into a header hw/intc/arm_gicv5: Correct offset for IRS_VMT_STATUSR hw/intc/arm_gicv5: Ask CPUs whether IRS needs virtualization support hw/intc/arm_gicv5: Indicate virtualization in ID registers hw/intc/arm_gicv5: Implement IRS_VMT_BASER and IRS_VMT_STATUSR hw/intc/arm_gicv5: IMplement IRS_VMT_CFGR hw/intc/arm_gicv5: Implement IRS_VMAP_L2_VMTR hw/intc/arm_gicv5: Implement IRS_VMAP_VMR hw/intc/arm_gicv5: Factor out code to fill in a GICv5ISTConfig hw/intc/arm_gicv5: Cache info about valid VMs in a hashtable hw/intc/arm_gicv5: Populate VM cache when VM table becomes valid hw/intc/arm_gicv5: Implement IRS_VMAP_VISTR hw/intc/arm_gicv5: Factor out "make an L2 IST valid" function hw/intc/arm_gicv5: Implement IRS_VMAP_L2_VISTR hw/intc/arm_gicv5: Cache VPE table information hw/intc/arm_gicv5: Implement IRS_VMAP_VPER hw/intc/arm_gicv5: Implement IRS_VPE_SELR and IRS_VPE_STATUSR hw/intc/arm_gicv5: Implement IRS_VPE_DBR hw/intc/arm_gicv5: Implement IRS_VPE_CR0 hw/intc/arm_gicv5: Implement gicv5_set_resident() hw/intc/arm_gicv5: Take cpuidx for stream commands on virtual interrupts hw/intc/arm_gicv5: Handle virtual=true in gicv5_set_priority() hw/intc/arm_gicv5: Handle virtual=true for setting enabled, pending, handling hw/intc/arm_gicv5: Handle virtual=true for setting pending hw/intc/arm_gicv5: Handle virtual=true in gicv5_set_target() hw/intc/arm_gicv5: Handle virtual=true in gicv5_deactivate() hw/intc/arm_gicv5: Handle activation of a virtual interrupt hw/intc/arm_gicv5: Handle virtual=true in gicv5_request_config() hw/intc/arm_gicv5: Implement irs_recalc_vhppi() hw/intc/arm_gicv5: Recalculate vHPPIs on VIST and VPE mapping hw/intc/arm_gicv5: Add virtual support to gicv5_get_hppi() hw/intc/arm_gicv5: Implement IRS_VPE_HPPIR hw/intc/arm_gicv5: Implement ringing doorbells for VPEs hw/intc/arm_gicv5: Handle vHPPIs when IRS_CR0.IRSEN is toggled hw/intc/arm_gicv5: Implement saving virtual interrupt state to guest memory hw/intc/arm_gicv5: Implement reporting of Quiesced state hw/intc/arm_gicv5: Implement no-passthrough IRS_SPI_VMR hw/arm/virt: allow virtualization=on with gicv5 hw/arm/virt.c | 5 +- hw/intc/arm_gicv5.c | 2554 +++++++++++++++++++++++----- hw/intc/arm_gicv5_common.c | 30 +- hw/intc/trace-events | 19 +- include/hw/intc/arm_gicv5.h | 18 + include/hw/intc/arm_gicv5_common.h | 40 +- include/hw/intc/arm_gicv5_regs.h | 325 ++++ include/hw/intc/arm_gicv5_stream.h | 81 +- target/arm/cpregs.h | 85 +- target/arm/cpu-features.h | 8 + target/arm/cpu.c | 72 +- target/arm/cpu.h | 33 +- target/arm/gicv5-stubs.c | 8 + target/arm/helper.c | 23 +- target/arm/internals.h | 23 + target/arm/tcg/gicv5-cpuif.c | 1390 +++++++++++++-- target/arm/tcg/trace-events | 10 +- 17 files changed, 4089 insertions(+), 635 deletions(-) create mode 100644 include/hw/intc/arm_gicv5_regs.h -- 2.43.0
