On 13/10/26 10:38, Peter Maydell wrote:
The GICv5 specification allows implementations to declare a
MIN_LPI_ID_BITS value in IST_IDR2, which specifies the minimum number
of supported LPIs which can be configured (both for physical LPIs and
for virtual LPIs in VMs). It also notes (I_ZKLJR) that it doesn't
expect most hardware implementations to require a minimum numberof
LPI ID bits, and that this is mostly useful for the virtual IRS that
a hypervisor might expose to a guest.
QEMU generally prefers to offer the guest the highest-flexibility
setting when it comes to this kind of IMPDEF value, so for instance
we set our supported ID and IAFFID bit size to the maximum the spec
permits. Since this value is a minimum rather than a maximum,
"highest-flexibility" means allowing the guest to configure a very
small LPI range if it wants to. Our current setting of 14 for
QEMU_GICV5_MIN_LPI_ID_BITS is the least-flexible the architecture
permits and requires that guests always configure large LPI ranges.
Set QEMU_GICV5_MIN_LPI_ID_BITS to 0, as the spec suggests real
hardware would.
Signed-off-by: Peter Maydell <[email protected]>
---
include/hw/intc/arm_gicv5_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Still valid with A.a release.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
