The scalar atomic instructions are able to perform a word or double-word read-modify-write atomically.
Signed-off-by: Brian Cain <[email protected]> --- target/hexagon/gen_tcg.h | 27 +++++++++++++++++++++ target/hexagon/genptr.h | 11 +++++++++ target/hexagon/attribs_def.h.inc | 1 + target/hexagon/genptr.c | 32 +++++++++++++++++++++++++ target/hexagon/tag_rev_info.c.inc | 15 ++++++++++++ target/hexagon/gen_idef_parser_funcs.py | 2 ++ target/hexagon/imported/encode_pp.def | 15 +++++++++++- target/hexagon/imported/ldst.idef | 15 ++++++++++++ target/hexagon/imported/macros.def | 10 ++++++++ target/hexagon/imported/system.idef | 1 + 10 files changed, 128 insertions(+), 1 deletion(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 80d8a7b6bac..38d8558c97a 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -100,6 +100,28 @@ #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ fGEN_TCG_LOAD_AP(RddV, 8, u) +#define fGEN_TCG_ATOMIC4(OP) \ + do { \ + fEA_REG(RsV); \ + gen_atomic4(ctx, RdV, EA, RtV, OP); \ + } while (0) +#define fGEN_TCG_AM_addw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_ADD) +#define fGEN_TCG_AM_addw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_ADD) +#define fGEN_TCG_AM_andw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_AND) +#define fGEN_TCG_AM_andw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_AND) +#define fGEN_TCG_AM_orw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_OR) +#define fGEN_TCG_AM_orw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_OR) +#define fGEN_TCG_AM_xorw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_XOR) +#define fGEN_TCG_AM_xorw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_XOR) +#define fGEN_TCG_AM_swapw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_SWAP) +#define fGEN_TCG_AM_swapw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_SWAP) +#define fGEN_TCG_AM_swapd_aq(SHORTCODE) \ + do { \ + fEA_REG(RsV); \ + gen_atomic8(ctx, RddV, EA, RttV); \ + } while (0) +#define fGEN_TCG_AM_swapd_rl(SHORTCODE) fGEN_TCG_AM_swapd_aq(SHORTCODE) + #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE @@ -1377,6 +1399,11 @@ RsV = RsV; \ uiV = uiV; \ } while (0) +#define fGEN_TCG_Y4_dcfetch_multi(SHORTCODE) \ + do { \ + RsV = RsV; \ + RtV = RtV; \ + } while (0) #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 238ee089cba..7c0e90e93aa 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -58,6 +58,17 @@ TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign); TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign); void gen_set_half(int N, TCGv result, TCGv src); void gen_set_half_i64(int N, TCGv_i64 result, TCGv src); +typedef enum { + HEX_ATOMIC_ADD, + HEX_ATOMIC_AND, + HEX_ATOMIC_OR, + HEX_ATOMIC_XOR, + HEX_ATOMIC_SWAP, +} HexAtomicOp; + +void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, + HexAtomicOp operation); +void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 src); void probe_noshuf_load(TCGv va, int s, int mi); void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc index 5a98ea33139..8deef8e4cfb 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -60,6 +60,7 @@ DEF_ATTRIB(COPBYADDRESS, "Cache operation by address", "", "") DEF_ATTRIB(COPBYIDX, "Cache operation by index", "", "") DEF_ATTRIB(RELEASE, "Releases a lock", "", "") DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "") +DEF_ATTRIB(ATOMIC, "Atomic memory instruction", "", "") DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "") DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "") diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 90197c6e72e..46ef5bd704d 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -668,6 +668,38 @@ static inline void gen_store_conditional8(DisasContext *ctx, tcg_gen_movi_tl(hex_llsc_addr, ~0); } +void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, + HexAtomicOp operation) +{ + MemOp memop = MO_LE | MO_32 | MO_ALIGN; + + switch (operation) { + case HEX_ATOMIC_ADD: + tcg_gen_atomic_fetch_add_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_AND: + tcg_gen_atomic_fetch_and_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_OR: + tcg_gen_atomic_fetch_or_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_XOR: + tcg_gen_atomic_fetch_xor_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_SWAP: + tcg_gen_atomic_xchg_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + default: + g_assert_not_reached(); + } +} + +void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 src) +{ + tcg_gen_atomic_xchg_i64(dest, vaddr, src, ctx->mem_idx, + MO_LE | MO_64 | MO_ALIGN); +} + #ifndef CONFIG_HEXAGON_IDEF_PARSER static TCGv gen_slotval(DisasContext *ctx) { diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc index b380a6b44ae..a1b7b50cbf2 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -698,6 +698,21 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = { .introduced = HEX_VER_V81, .removed = HEX_VER_NONE }, [V6_vconv_bf_qf32] = { .introduced = HEX_VER_V81, .removed = HEX_VER_NONE }, + + [Y4_dcfetch_multi] = { .introduced = HEX_VER_V85, + .removed = HEX_VER_NONE }, + [AM_addw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_addw_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_andw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_andw_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_orw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_orw_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_swapd_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_swapd_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_swapw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_swapw_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_xorw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, + [AM_xorw_rl] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, }; #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py index 32bce9b0028..7151a4f6713 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -68,6 +68,8 @@ def main(): ## Skip the guest instructions if "A_GUEST" in hex_common.attribdict[tag]: continue + if "A_ATOMIC" in hex_common.attribdict[tag]: + continue ## Skip instructions that saturate in a ternary expression if tag in {"S2_asr_r_r_sat", "S2_asl_r_r_sat"}: continue diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def index 4b307b97b30..c590ed4f959 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -406,7 +406,8 @@ DEF_ENC32(R6_release_at_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --0011dd") DEF_ENC32(R6_release_st_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --1011dd") DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii 001iiiii") -DEF_ENC32(Y2_dcfetchbo, ICLASS_LD" 010 0 000 sssss PP0--iii iiiiiiii") +DEF_ENC32(Y2_dcfetchbo, "10010100000sssssPP000iiiiiiiiiii") +DEF_ENC32(Y4_dcfetch_multi,"10010100000sssssPP001ttttt------") DEF_ENC32(Y2_dcfetchbo_nt,"10010100000sssssPP10-iiiiiiiiiii") @@ -1895,6 +1896,18 @@ SH_RRR_ENC(S2_cabacdecbin, "0001","11-","-","11-","ddddd") /* implicit P0 w DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rdd=(Rss,Rtt,Pu)") +DEF_ENC32(AM_addw_aq, "10010000000sssssPP1ttttt001ddddd") +DEF_ENC32(AM_addw_rl, "10010000000sssssPP1ttttt010ddddd") +DEF_ENC32(AM_andw_aq, "10010000000sssssPP1ttttt101ddddd") +DEF_ENC32(AM_andw_rl, "10010000000sssssPP1ttttt110ddddd") +DEF_ENC32(AM_orw_aq, "10010000110sssssPP0ttttt001ddddd") +DEF_ENC32(AM_orw_rl, "10010000110sssssPP0ttttt010ddddd") +DEF_ENC32(AM_xorw_aq, "10010000110sssssPP0ttttt101ddddd") +DEF_ENC32(AM_xorw_rl, "10010000110sssssPP0ttttt110ddddd") +DEF_ENC32(AM_swapw_aq, "10010000110sssssPP1ttttt001ddddd") +DEF_ENC32(AM_swapw_rl, "10010000110sssssPP1ttttt010ddddd") +DEF_ENC32(AM_swapd_aq, "10010000110sssssPP1ttttt101ddddd") +DEF_ENC32(AM_swapd_rl, "10010000110sssssPP1ttttt110ddddd") SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ldst.idef index 7106a0c572c..a08d2138152 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -135,6 +135,8 @@ STD_ST_AMODES(storerhnew, "Nt8.new", "memh","Store Half integer",ATTRIBS(A_REGWR Q6INSN(S2_allocframe,"allocframe(Rx32,#u11:3):raw", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY), "Allocate stack frame", { fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA); RxV = EA-uiV; }) +Q6INSN(S2_allocframe_rb,"allocframe_rb(Rx32,#u11:3):raw", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY,A_RESTRICT_TARGET), "Allocate stack frame", +{ fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA); RxV = EA-uiV; }) #define A_RETURN A_RESTRICT_COF_MAX1,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOSLOT1_STORE,A_RET_TYPE,A_DEALLOCRET @@ -156,6 +158,19 @@ Q6INSN(S4_stored_rl_at_vi,"memd_rl(Rs32):at=Rtt32",ATTRIBS(A_REGWRSIZE_8B,A_RELE Q6INSN(S2_storew_rl_st_vi,"memw_rl(Rs32):st=Rt32",ATTRIBS(A_REGWRSIZE_4B,A_RELEASE,A_VTCM_ALLBANK_ACCESS,A_RLS_INNER,A_RLS_SAME_THREAD,A_RESTRICT_NOPACKET,A_MEMSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { fEA_REG(RsV); fSTORE(1,4,EA,RtV); }) Q6INSN(S4_stored_rl_st_vi,"memd_rl(Rs32):st=Rtt32",ATTRIBS(A_REGWRSIZE_8B,A_RELEASE,A_VTCM_ALLBANK_ACCESS,A_RLS_INNER,A_RLS_SAME_THREAD,A_RESTRICT_NOPACKET,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Double integer", { fEA_REG(RsV); fSTORE(1,8,EA,RttV); }) +Q6INSN(AM_addw_aq,"Rd32=atomw_add(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic add word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,0,*EA+RtV); }) +Q6INSN(AM_addw_rl,"Rd32=atomw_add(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic add word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,0,*EA+RtV); }) +Q6INSN(AM_andw_aq,"Rd32=atomw_and(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic and word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,1,*EA&RtV); }) +Q6INSN(AM_andw_rl,"Rd32=atomw_and(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic and word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,1,*EA&RtV); }) +Q6INSN(AM_orw_aq,"Rd32=atomw_or(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic or word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,2,*EA|RtV); }) +Q6INSN(AM_orw_rl,"Rd32=atomw_or(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic or word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,2,*EA|RtV); }) +Q6INSN(AM_xorw_aq,"Rd32=atomw_xor(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic xor word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,3,*EA^RtV); }) +Q6INSN(AM_xorw_rl,"Rd32=atomw_xor(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic xor word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,3,*EA^RtV); }) +Q6INSN(AM_swapw_aq,"Rd32=atomw_swap(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic swap word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,4,RtV); }) +Q6INSN(AM_swapw_rl,"Rd32=atomw_swap(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic swap word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,4,RtV); }) +Q6INSN(AM_swapd_aq,"Rdd32=atomd_swap(Rs32,Rtt32):aq",ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic swap double word acquire",{ fEA_REG(RsV); fATOMIC_LDST(8,RddV,EA,RttV,4,RttV); }) +Q6INSN(AM_swapd_rl,"Rdd32=atomd_swap(Rs32,Rtt32):rl",ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),"Atomic swap double word release",{ fEA_REG(RsV); fATOMIC_LDST(8,RddV,EA,RttV,4,RttV); }) + Q6INSN(L2_deallocframe,"Rdd32=deallocframe(Rs32):raw", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_LOAD,A_DEALLOCFRAME), "Deallocate stack frame", { fHIDE(size8u_t tmp;) fEA_REG(RsV); fLOAD(1,8,u,EA,tmp); diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/macros.def index 13eb13c71f7..ef9955a0212 100644 --- a/target/hexagon/imported/macros.def +++ b/target/hexagon/imported/macros.def @@ -1404,6 +1404,11 @@ DEF_MACRO(fLOAD_LOCKED, (A_LOAD,A_MEMLIKE) ) +DEF_MACRO(fATOMIC_LDST, + { }, + (A_LOAD,A_STORE,A_MEMLIKE) +) + DEF_MACRO(fSTORE, { MEM_STORE##SIZE(thread,EA,SRC,insn); }, (A_STORE,A_MEMLIKE) @@ -1958,6 +1963,11 @@ DEF_MACRO(fDCFETCH, (A_MEMLIKE) ) +DEF_MACRO(fDCFETCH_MULTI, + { }, + (A_MEMLIKE) +) + DEF_MACRO(fICINVA, /* */, (A_ICINVA) diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/system.idef index a58da8f8269..9c4897a2eee 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -241,6 +241,7 @@ Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET, Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);}) Q6INSN(Y2_dcfetchbo_nt,"dcfetch(Rs32+#u11:3):nt",ATTRIBS(A_NA_NT,A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);}) +Q6INSN(Y4_dcfetch_multi,"dcfetch_multi(Rs32,Rt32)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_REG(RsV); fDCFETCH_MULTI(EA,fEXTRACTU_BITS(RtV,10,0));}) Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Invalidate",{fDCKILL();}) -- 2.34.1
