Signed-off-by: Brian Cain <[email protected]>
---
include/hw/hexagon/hexagon.h | 6 ++--
hw/hexagon/machine_cfg_v85na_1.h.inc | 50 +++++++++++++++++++++++++++
hw/hexagon/machine_cfg_v85qa_1.h.inc | 51 ++++++++++++++++++++++++++++
hw/hexagon/hexagon_dsp.c | 48 +++++++++++++++++++++++++-
4 files changed, 152 insertions(+), 3 deletions(-)
create mode 100644 hw/hexagon/machine_cfg_v85na_1.h.inc
create mode 100644 hw/hexagon/machine_cfg_v85qa_1.h.inc
diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h
index 9b5d33ffc3b..ffd9967330f 100644
--- a/include/hw/hexagon/hexagon.h
+++ b/include/hw/hexagon/hexagon.h
@@ -29,9 +29,11 @@ typedef enum {
v73m_rev = 0xcc73,
v81_rev = 0x8781,
v81dgb_1_rev = 0xcc81,
+ v85qa_1_rev = 0x8185,
+ v85na_1_rev = 0x8085,
} Rev_t;
-#define HEXAGON_LATEST_REV v73
-#define HEXAGON_LATEST_REV_UPPER V73
+#define HEXAGON_LATEST_REV v85
+#define HEXAGON_LATEST_REV_UPPER V85
/*
* Config table address bases represent bits [35:16].
diff --git a/hw/hexagon/machine_cfg_v85na_1.h.inc
b/hw/hexagon/machine_cfg_v85na_1.h.inc
new file mode 100644
index 00000000000..f0ea1be1039
--- /dev/null
+++ b/hw/hexagon/machine_cfg_v85na_1.h.inc
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+static const struct hexagon_machine_config v85na_1 = {
+ .cfgbase = 0xd8180000,
+ .l2tcm_size = 0x00000000,
+ .l2vic_base = 0xfc910000,
+ .l2vic_size = 0x00001000,
+ .csr_base = 0xfc900000,
+ .qtmr_region = 0xfc921000,
+ .cfgtable = {
+ .l2tcm_base = 0x0000d800,
+ .subsystem_base = 0x00002000,
+ .etm_base = 0x0000d819,
+ .l2cfg_base = 0x0000d81a,
+ .reserved1 = 0x0000d81b,
+ .l1s0_base = 0x0000d900,
+ .fastl2vic_base = 0x0000d81e,
+ .jtlb_size_entries = 0x00000080,
+ .coproc_present = 0x0000001d,
+ .ext_contexts = 0x00000008,
+ .vtcm_base = 0x0000d900,
+ .vtcm_size_kb = 0x00003000,
+ .l2tag_size = 0x00000400,
+ .l2ecomem_size = 0x00000400,
+ .thread_enable_mask = 0x00000fff,
+ .l2line_size = 0x00000080,
+ .l2itcm_base = 0x0000d800,
+ .dma_version = 0x0000000c,
+ .hvx_vec_log_length = 0x00000007,
+ .coproc2_reg0 = 0x00000010,
+ .coproc2_reg1 = 0x00000008,
+ .coproc2_reg2 = 0x00000003,
+ .acd_preset = 0x00000001,
+ .mnd_preset = 0x00000001,
+ .l1d_size_kb = 0x00000040,
+ .l1i_size_kb = 0x00000040,
+ .l1d_write_policy = 0x00000002,
+ .vtcm_bank_width = 0x00000080,
+ .consistency_domain = 0x000000e0,
+ .capacity_domain = 0x00000080,
+ .axi3_lowaddr = 0x00004000,
+ .corecfg_present = 0x0000000d,
+ .coproc2_fp16_acc_exp = 0x00000003,
+ .AXIM_data_width = 0x00000100,
+ .l1d_ways = 0x00000008,
+ .l1i_ways = 0x00000004,
+ .l2way_num = 0x00000008,
+ .dma_jtlb_entries = 0x00000040,
+ },
+};
diff --git a/hw/hexagon/machine_cfg_v85qa_1.h.inc
b/hw/hexagon/machine_cfg_v85qa_1.h.inc
new file mode 100644
index 00000000000..916a91ee291
--- /dev/null
+++ b/hw/hexagon/machine_cfg_v85qa_1.h.inc
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+static const struct hexagon_machine_config v85qa_1 = {
+ .cfgbase = 0xd8180000,
+ .l2tcm_size = 0x00000000,
+ .l2vic_base = 0xfc910000,
+ .l2vic_size = 0x00001000,
+ .csr_base = 0xfc900000,
+ .qtmr_region = 0xfc921000,
+ .cfgtable = {
+ .l2tcm_base = 0x0000d800,
+ .subsystem_base = 0x0000fc90,
+ .etm_base = 0x0000d819,
+ .l2cfg_base = 0x0000d81a,
+ .reserved1 = 0x0000d81b,
+ .l1s0_base = 0x0000d900,
+ .fastl2vic_base = 0x0000d81e,
+ .jtlb_size_entries = 0x00000080,
+ .coproc_present = 0x0000001d,
+ .ext_contexts = 0x00000008,
+ .vtcm_base = 0x0000d900,
+ .vtcm_size_kb = 0x00004000,
+ .l2tag_size = 0x00000400,
+ .l2ecomem_size = 0x00000400,
+ .thread_enable_mask = 0x00000fff,
+ .eccreg_base = 0x0000d81f,
+ .l2line_size = 0x00000080,
+ .l2itcm_base = 0x0000d800,
+ .dma_version = 0x0000000c,
+ .hvx_vec_log_length = 0x00000007,
+ .coproc2_reg0 = 0x00000010,
+ .coproc2_reg1 = 0x00000008,
+ .coproc2_reg2 = 0x00000003,
+ .acd_preset = 0x00000001,
+ .mnd_preset = 0x00000001,
+ .l1d_size_kb = 0x00000040,
+ .l1i_size_kb = 0x00000040,
+ .l1d_write_policy = 0x00000002,
+ .vtcm_bank_width = 0x00000080,
+ .consistency_domain = 0x000000e0,
+ .capacity_domain = 0x00000080,
+ .axi3_lowaddr = 0x00004000,
+ .corecfg_present = 0x0000000d,
+ .coproc2_fp16_acc_exp = 0x00000003,
+ .AXIM_data_width = 0x00000100,
+ .l1d_ways = 0x00000008,
+ .l1i_ways = 0x00000004,
+ .l2way_num = 0x00000008,
+ .dma_jtlb_entries = 0x00000040,
+ },
+};
diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c
index 8824fe10a59..28b5cf39917 100644
--- a/hw/hexagon/hexagon_dsp.c
+++ b/hw/hexagon/hexagon_dsp.c
@@ -32,6 +32,8 @@
#include "machine_cfg_v68n_1024.h.inc"
#include "machine_cfg_v81dgb_1.h.inc"
#include "machine_cfg_v81qa_1.h.inc"
+#include "machine_cfg_v85na_1.h.inc"
+#include "machine_cfg_v85qa_1.h.inc"
#define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine"
OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE)
@@ -227,7 +229,6 @@ static void v81qa_1_init(ObjectClass *oc, const void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Hexagon V81QA_1";
- mc->alias = "sim";
mc->init = v81qa_1_config_init;
init_mc(mc);
mc->default_cpu_type = TYPE_HEXAGON_CPU_V81;
@@ -235,6 +236,41 @@ static void v81qa_1_init(ObjectClass *oc, const void *data)
mc->default_cpus = 12;
}
+static void v85qa_1_config_init(MachineState *machine)
+{
+ hexagon_common_init(machine, v85qa_1_rev, &v85qa_1);
+}
+
+static void v85qa_1_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Hexagon V85QA_1";
+ mc->init = v85qa_1_config_init;
+ init_mc(mc);
+ mc->default_cpu_type = TYPE_HEXAGON_CPU_V85;
+ mc->max_cpus = 12;
+ mc->default_cpus = 12;
+}
+
+static void v85na_1_config_init(MachineState *machine)
+{
+ hexagon_common_init(machine, v85na_1_rev, &v85na_1);
+}
+
+static void v85na_1_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Hexagon V85NA_1";
+ mc->alias = "sim";
+ mc->init = v85na_1_config_init;
+ init_mc(mc);
+ mc->default_cpu_type = TYPE_HEXAGON_CPU_V85;
+ mc->max_cpus = 12;
+ mc->default_cpus = 12;
+}
+
static const TypeInfo hexagon_machine_types[] = {
{
.name = TYPE_HEXAGON_COMMON_MACHINE,
@@ -268,6 +304,16 @@ static const TypeInfo hexagon_machine_types[] = {
.parent = TYPE_HEXAGON_DSP_MACHINE,
.class_init = v81qa_1_init,
},
+ {
+ .name = MACHINE_TYPE_NAME("V85QA_1"),
+ .parent = TYPE_HEXAGON_DSP_MACHINE,
+ .class_init = v85qa_1_init,
+ },
+ {
+ .name = MACHINE_TYPE_NAME("V85NA_1"),
+ .parent = TYPE_HEXAGON_DSP_MACHINE,
+ .class_init = v85na_1_init,
+ },
};
DEFINE_TYPES(hexagon_machine_types)
--
2.34.1
