Add the RISC-V IOMMU UAPI needed by the accelerated IOMMU device. Only the RISC-V IOMMU definitions of iommufd.h are taken, instead of doing a full scripts/update-linux-headers.sh sync that would also pull in unrelated changes.
The kernel UAPI this is taken from is not upstream yet, so this import is a placeholder and will be replaced by a regular linux-headers sync once the kernel patches are merged. Signed-off-by: Gong Shuai <[email protected]> --- linux-headers/linux/iommufd.h | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h index 3c61caadbf..c6a3204fe0 100644 --- a/linux-headers/linux/iommufd.h +++ b/linux-headers/linux/iommufd.h @@ -506,18 +506,31 @@ struct iommu_hwpt_amd_guest { __aligned_u64 dte[4]; }; +/** + * struct iommu_hwpt_riscv - RISC-V IOMMU stage-1 page table data + * (IOMMU_HWPT_DATA_RISCV_S1) + * @tc: Guest device context translation control + * @iosatp: Guest device context stage-1 root page table pointer + */ +struct iommu_hwpt_riscv { + __aligned_u64 tc; + __aligned_u64 iosatp; +}; + /** * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table * @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table + * @IOMMU_HWPT_DATA_RISCV_S1: RISC-V IOMMU stage-1 page table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE = 0, IOMMU_HWPT_DATA_VTD_S1 = 1, IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, IOMMU_HWPT_DATA_AMD_GUEST = 3, + IOMMU_HWPT_DATA_RISCV_S1 = 4, }; /** @@ -703,6 +716,14 @@ struct iommu_hw_info_amd { __aligned_u64 efr2; }; +/** + * struct iommu_hw_info_riscv - RISC-V IOMMU device info + * @capabilities: Value of RISC-V IOMMU Capabilities register + */ +struct iommu_hw_info_riscv { + __u64 capabilities; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware @@ -713,6 +734,7 @@ struct iommu_hw_info_amd { * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) info type * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type + * @IOMMU_HW_INFO_TYPE_RISCV: RISC-V IOMMU info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE = 0, @@ -721,6 +743,7 @@ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, IOMMU_HW_INFO_TYPE_AMD = 4, + IOMMU_HW_INFO_TYPE_RISCV = 5, }; /** @@ -890,10 +913,12 @@ struct iommu_hwpt_get_dirty_bitmap { * Data Type * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1 * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3 + * @IOMMU_VIOMMU_INVALIDATE_DATA_RISCV: Invalidation data for RISC-V IOMMU */ enum iommu_hwpt_invalidate_data_type { IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0, IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1, + IOMMU_VIOMMU_INVALIDATE_DATA_RISCV = 2, }; /** @@ -954,6 +979,31 @@ struct iommu_viommu_arm_smmuv3_invalidate { __aligned_le64 cmd[2]; }; +/** + * struct iommu_viommu_riscv_invalidate - RISC-V IOMMU cache invalidation + * (IOMMU_VIOMMU_INVALIDATE_DATA_RISCV) + * @cmd: 128-bit cache invalidation command that runs in the IOMMU command + * queue, in the format defined by the "IOMMU Page-table cache + * invalidation" section of the RISC-V IOMMU specification. Must be + * little-endian. + * + * Supported command list only when passing in a vIOMMU via @hwpt_id: + * IOTINVAL.VMA + * + * The isolation operands are owned by the kernel, which overwrites them + * before the command is issued: + * GV = 1 and GSCID = the GSCID assigned to the vIOMMU + * PSCV = 1 and PSCID = 0 + * + * All other reserved bits must be 0. + * + * -EIO will be returned if the command is not supported, -EINVAL if it is + * malformed. + */ +struct iommu_viommu_riscv_invalidate { + __aligned_le64 cmd[2]; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -1095,6 +1145,7 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_RISCV: RISC-V IOMMU driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, @@ -1105,6 +1156,7 @@ enum iommu_viommu_type { * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register */ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, + IOMMU_VIOMMU_TYPE_RISCV = 3, }; /** -- 2.53.0
