The envcfg CBO fields are provided by Zicbom and Zicboz. Keep them read-only zero when the corresponding extension is absent in all three envcfg CSRs. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4225
Signed-off-by: wangyang <[email protected]> --- target/riscv/tcg/csr.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 061bc9d..ba68c25 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3224,10 +3224,19 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | - MENVCFG_CBZE; + uint64_t mask = MENVCFG_FIOM; bool stce_changed = false; + /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */ + if (cfg->ext_zicbom) { + mask |= MENVCFG_CBIE | MENVCFG_CBCFE; + } + + /* CBZE is read-only zero when Zicboz is not implemented. */ + if (cfg->ext_zicboz) { + mask |= MENVCFG_CBZE; + } + /* * menvcfg.LPE (Zicfilp) and menvcfg.SSE (Zicfiss) reside in the low * 32 bits and are defined for both RV32 and RV64, so they must be @@ -3386,10 +3395,20 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); - uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + uint64_t mask = HENVCFG_FIOM; RISCVException ret; bool stce_changed = false; + /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */ + if (cfg->ext_zicbom) { + mask |= HENVCFG_CBIE | HENVCFG_CBCFE; + } + + /* CBZE is read-only zero when Zicboz is not implemented. */ + if (cfg->ext_zicboz) { + mask |= HENVCFG_CBZE; + } + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret != RISCV_EXCP_NONE) { return ret; -- 2.43.0
