On 14/10/26 23:05, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier <[email protected]> --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd8..00650a66dcb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; }
Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC: https://lore.kernel.org/qemu-devel/[email protected]/ Anyway, Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
