The following changes since commit c61ea024f6d58261394b1b408e0f220e30c136a4:

  Merge tag 'qemu-macppc-20261013' of https://github.com/mcayland/qemu into 
staging (2026-10-14 10:04:07 +0200)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20261015

for you to fetch changes up to 512b06299114d08458019a6c3944f73ae26cb5fc:

  tcg/riscv64: Fall back when AUIPC pairs are out of range (2026-10-15 11:54:47 
+0200)

----------------------------------------------------------------
tcg: Introduce tcg_type_bits() helper
tcg/riscv64: Remove vector min/max ops with immediates
tcg/optimize: Do not derive s_mask from rotated s_mask
tcg/aarch64/tcg-target.c.inc: Correct register MIN/MAX instuctions
tcg/riscv64: Validate AUIPC relocation range

----------------------------------------------------------------
Aurelien Jarno (1):
      tcg/riscv64: Remove vector min/max ops with immediates

Dominic P (2):
      tcg/optimize: Do not derive s_mask from rotated s_mask
      tests/tcg: Add tests for sign extension after rotate

Jim MacArthur (1):
      tcg/aarch64/tcg-target.c.inc: Correct register MIN/MAX instuctions

Max Chou (2):
      tcg/riscv64: Validate AUIPC relocation range
      tcg/riscv64: Fall back when AUIPC pairs are out of range

Philippe Mathieu-Daudé (1):
      tcg: Introduce tcg_type_bits() helper

Richard Henderson (9):
      tcg/riscv64: Return tcg_insn_unit from insn encoders
      tcg/riscv64: Rename sb-type to b-type format
      tcg/riscv64: Rename uj-type to j-type format
      tcg/riscv64: Use signed type for encoding immediates
      tcg/riscv64: Adjust sign of lui immediate in tcg_out_movi
      tcg/riscv64: Assert immediate in range for {i,s,u,vi}-type insns
      tcg/riscv64: Return success from encode_jimm
      tcg/riscv64: Return success from encode_bimm
      tcg/riscv64: Fix off-by-one in branch range tests

 include/tcg/tcg.h                  |  11 ++
 tcg/optimize.c                     |  23 +++-
 tcg/tcg.c                          |   4 +-
 tests/tcg/arm/test-arm-opt-ror.c   |  21 +++
 tests/tcg/i386/test-i386-opt-rol.c |  21 +++
 tcg/aarch64/tcg-target.c.inc       |   8 +-
 tcg/riscv64/tcg-target.c.inc       | 253 +++++++++++++++++++------------------
 tests/tcg/arm/meson.build          |   1 +
 tests/tcg/i386/meson.build         |   1 +
 9 files changed, 208 insertions(+), 135 deletions(-)
 create mode 100644 tests/tcg/arm/test-arm-opt-ror.c
 create mode 100644 tests/tcg/i386/test-i386-opt-rol.c

Reply via email to