Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
---
target/hexagon/cpu.h | 2 -
target/hexagon/cpu_helper.h | 6 ---
target/hexagon/translate.h | 2 -
target/hexagon/cpu.c | 1 -
target/hexagon/cpu_helper.c | 79 -------------------------------------
target/hexagon/machine.c | 2 +-
target/hexagon/translate.c | 21 ----------
7 files changed, 1 insertion(+), 112 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 65fd2b29830..2da3b586b5a 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -151,7 +151,6 @@ typedef struct CPUArchState {
hex_lock_state_t k0_lock_state;
uint32_t tlb_lock_count;
uint32_t k0_lock_count;
- uint64_t t_cycle_count;
#endif
uint32_t imprecise_exception;
target_ulong new_value_usr;
@@ -226,7 +225,6 @@ static inline HexagonHVXContext *hex_hvx(CPUHexagonState
*env)
FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
FIELD(TB_FLAGS, MMU_INDEX, 1, 3)
-FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)
FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1)
G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index 95a8f6587b6..8b1fb98a51a 100644
--- a/target/hexagon/cpu_helper.h
+++ b/target/hexagon/cpu_helper.h
@@ -24,11 +24,5 @@ void hexagon_start_threads(CPUHexagonState *env, uint32_t
mask);
void hexagon_stop_thread(CPUHexagonState *env);
void hexagon_nmi(CPUHexagonState *env, uint32_t thread_mask);
void hexagon_resume_threads(CPUHexagonState *env, uint32_t mask);
-uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env);
-uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env);
-uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env);
-void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val);
-void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val);
-void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val);
#endif
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 2d1ed5208b7..ccf9d52997a 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -97,10 +97,8 @@ typedef struct DisasContext {
TCGv new_pred_value[NUM_PREGS];
TCGv branch_taken;
TCGv dczero_addr;
- bool pcycle_enabled;
bool hvx_coproc_enabled;
bool hvx_check_emitted;
- uint32_t num_cycles;
} DisasContext;
bool is_gather_store_insn(DisasContext *ctx);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 6550e7fa800..1bdc3d8aed6 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -349,7 +349,6 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)
cpu = env_archcpu(env);
hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX,
cpu_mmu_index(env_cpu(env), false));
- hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1);
hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED,
cpu->hvx_ctx[0] &&
GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]));
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index c2fc27f1c02..1fdd81ad9b4 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -132,85 +132,6 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env,
int index)
g_assert_not_reached();
}
-uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env)
-{
- uint64_t total = 0;
- CPUState *cs;
-
- BQL_LOCK_GUARD();
- CPU_FOREACH(cs) {
- CPUHexagonState *thread_env = cpu_env(cs);
- total += thread_env->t_cycle_count;
- }
- return total;
-}
-
-uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env)
-{
- return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32);
-}
-
-uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env)
-{
- return (uint32_t)(hexagon_get_sys_pcycle_count(env));
-}
-
-/*
- * Every function in this family takes the BQL itself, so the guard below
- * holds it across the read-modify-write. Nested guards are no-ops.
- */
-void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val)
-{
- uint64_t old;
-
- BQL_LOCK_GUARD();
- old = hexagon_get_sys_pcycle_count(env);
- old = deposit64(old, 32, 32, val);
- hexagon_set_sys_pcycle_count(env, old);
-}
-
-void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val)
-{
- uint64_t old;
-
- BQL_LOCK_GUARD();
- old = hexagon_get_sys_pcycle_count(env);
- old = deposit64(old, 0, 32, val);
- hexagon_set_sys_pcycle_count(env, old);
-}
-
-void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val)
-{
- CPUState *cs;
- uint64_t total;
- int num_threads;
- int64_t delta, per_thread, remainder;
-
- BQL_LOCK_GUARD();
- total = hexagon_get_sys_pcycle_count(env);
-
- /* Count active threads */
- num_threads = 0;
- CPU_FOREACH(cs) {
- num_threads++;
- }
- g_assert(num_threads > 0);
-
- /*
- * Distribute the delta evenly across all threads.
- * Any remainder goes to the calling thread.
- */
- delta = (int64_t)(val - total);
- per_thread = delta / num_threads;
- remainder = delta - per_thread * num_threads;
-
- CPU_FOREACH(cs) {
- CPUHexagonState *thread_env = cpu_env(cs);
- thread_env->t_cycle_count += per_thread;
- }
- env->t_cycle_count += remainder;
-}
-
static void hexagon_resume_thread(CPUHexagonState *env)
{
CPUState *cs = env_cpu(env);
diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c
index f3e97224d81..36fee33d333 100644
--- a/target/hexagon/machine.c
+++ b/target/hexagon/machine.c
@@ -35,7 +35,7 @@ const VMStateDescription vmstate_hexagon_cpu = {
VMSTATE_UINT32(env.k0_lock_count, HexagonCPU),
VMSTATE_UINT32(env.threadId, HexagonCPU),
VMSTATE_UINT32(env.cause_code, HexagonCPU),
- VMSTATE_UINT64(env.t_cycle_count, HexagonCPU),
+ VMSTATE_UNUSED(sizeof(uint64_t)),
VMSTATE_UINT32(env.imprecise_exception, HexagonCPU),
VMSTATE_END_OF_LIST()
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index cd1abdf1461..beee09bc4cb 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -63,7 +63,6 @@ TCGv hex_llsc_addr;
TCGv hex_llsc_val;
TCGv_i64 hex_llsc_val_i64;
#ifndef CONFIG_USER_ONLY
-TCGv_i64 hex_cycle_count;
TCGv hex_imprecise_exception;
#endif
TCGv hex_vstore_addr[VSTORES_MAX];
@@ -144,16 +143,6 @@ static void gen_precise_exception(int cause, uint32_t PC)
tcg_constant_i32(PC));
}
-#ifndef CONFIG_USER_ONLY
-static void gen_pcycle_counters(DisasContext *ctx)
-{
- if (ctx->pcycle_enabled) {
- tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles);
- }
-}
-#endif
-
-
static void gen_exec_counters(DisasContext *ctx)
{
tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
@@ -162,9 +151,6 @@ static void gen_exec_counters(DisasContext *ctx)
hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT],
hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns);
-#ifndef CONFIG_USER_ONLY
- gen_pcycle_counters(ctx);
-#endif
}
static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
@@ -1128,8 +1114,6 @@ static void gen_commit_hvx(DisasContext *ctx)
}
}
-#define PCYCLES_PER_PACKET 1
-
static void update_exec_counters(DisasContext *ctx)
{
int num_real_insns = 0;
@@ -1149,7 +1133,6 @@ static void update_exec_counters(DisasContext *ctx)
ctx->num_packets++;
ctx->num_insns += num_real_insns;
ctx->num_hvx_insns += num_hvx_insns;
- ctx->num_cycles += PCYCLES_PER_PACKET;
}
#ifndef CONFIG_USER_ONLY
@@ -1335,8 +1318,6 @@ static void
hexagon_tr_init_disas_context(DisasContextBase *dcbase,
ctx->hex_def = HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def;
ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;
#ifndef CONFIG_USER_ONLY
- ctx->num_cycles = 0;
- ctx->pcycle_enabled = FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED);
ctx->hvx_coproc_enabled =
FIELD_EX32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED);
ctx->hvx_check_emitted = false;
@@ -1489,8 +1470,6 @@ void hexagon_translate_init(void)
hex_cause_code = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUHexagonState, cause_code), "cause_code");
#ifndef CONFIG_USER_ONLY
- hex_cycle_count = tcg_global_mem_new_i64(tcg_env,
- offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count");
hex_imprecise_exception = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, imprecise_exception), "imprecise_exception");
#endif
--
2.34.1
