From: Anirudh Srinivasan <[email protected]> Now that we have the PRCM modelled, update the DT nodes for UART1 and the 5 I2C controllers to use the rcpu_prcm as a clock provider. This also allows us to eliminate the periph_clk that was added to the DT previously.
Signed-off-by: Anirudh Srinivasan <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- include/hw/riscv/tt_atlantis.h | 6 ++++++ hw/riscv/tt_atlantis.c | 23 ++++++++++++++--------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index db1dfed157..577c867d71 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -99,6 +99,12 @@ enum { TT_ATL_CLK_RCPU_ROOT = 1, TT_ATL_CLK_NOC_PLL = 25, TT_ATL_CLK_NOCC_CLK = 26, + TT_ATL_CLK_I2C0_PCLK = 33, + TT_ATL_CLK_I2C1_PCLK = 34, + TT_ATL_CLK_I2C2_PCLK = 35, + TT_ATL_CLK_I2C3_PCLK = 36, + TT_ATL_CLK_I2C4_PCLK = 37, + TT_ATL_CLK_UART1_PCLK = 39, TT_ATL_CLK_HSIO_PLL = 54, TT_ATL_CLK_PCIE_PLL = 55, TT_ATL_CLK_MM_PLL0 = 56, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 10ae3c2850..4e6c39982c 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -265,7 +265,8 @@ static void create_fdt_cpu(void *fdt, TTAtlantisSoCState *s, } static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, - int irqchip_phandle) + int irqchip_phandle, uint32_t clk_parent_phandle, + uint32_t clk_phandle) { g_autofree char *name = g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); @@ -275,6 +276,8 @@ static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size); qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); @@ -305,7 +308,9 @@ static void create_fdt_clk(void *fdt, const char *clock_name, } static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, - uint32_t irqchip_phandle, uint32_t clk_phandle) + uint32_t irqchip_phandle, + uint32_t clk_parent_phandle, + uint32_t clk_phandle) { g_autofree char *name = g_strdup_printf("/soc/i2c@%"HWADDR_PRIX, mem->base); @@ -314,7 +319,8 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); - qemu_fdt_setprop_cell(fdt, name, "clocks", clk_phandle); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 100000); qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); @@ -356,7 +362,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle = next_phandle(); uint32_t imsic_s_phandle = next_phandle(); - uint32_t periph_clk_phandle = next_phandle(); uint32_t osc_24m_phandle = next_phandle(); uint32_t prcm_rcpu_phandle; g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; @@ -372,10 +377,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) * aplic_s_phandle); */ - create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, - aplic_s_phandle); - - create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); create_fdt_clk(fdt, "osc-24m", 24000000, osc_24m_phandle); rcpu_name = create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_RCPU], "rcpu"); @@ -401,11 +402,15 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL0, prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL1); + create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, + aplic_s_phandle, prcm_rcpu_phandle, TT_ATL_CLK_UART1_PCLK); + for (int i = 0; i < TT_ATL_NUM_I2C; i++) { create_fdt_i2c(fdt, &s->memmap[TT_ATL_I2C0 + i], TT_ATL_I2C0_IRQ + i, - aplic_s_phandle, periph_clk_phandle); + aplic_s_phandle, prcm_rcpu_phandle, + TT_ATL_CLK_I2C0_PCLK + i); } /* I2C peripherals: qemu specific */ -- 2.55.0
