From: Anirudh Srinivasan <[email protected]> Atlantis has 4 PRCMs that are visible from S mode by the Ascalon Core (RCPU, HSIO, PCIe and MM). The remaining 2 are only accessed by the boot cpu which isn't modelled yet.
This commit adds these 4 PRCM blocks to the tt-atlantis model, along with necessary device tree nodes for them. Reviewed-by: Chao Liu <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Anirudh Srinivasan <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- docs/system/riscv/tt_atlantis.rst | 1 + include/hw/riscv/tt_atlantis.h | 22 +++++++ hw/riscv/tt_atlantis.c | 104 ++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlantis.rst index 1f2880d617..539c22354f 100644 --- a/docs/system/riscv/tt_atlantis.rst +++ b/docs/system/riscv/tt_atlantis.rst @@ -14,6 +14,7 @@ tt-atlantis QEMU model features * 8-core Ascalon-X CPU Cluster * RISC-V compliant Advanced Interrupt Architecture * 16550A compatible UART +* 4 PRCMs (Clock and Reset Controllers) Known limitations ----------------- diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 3923308b7c..db1dfed157 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -14,6 +14,7 @@ #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" #include "hw/riscv/riscv_hart.h" #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -23,6 +24,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) #define TT_ATL_NUM_I2C 5 +#define TT_ATL_NUM_PRCM 4 struct TTAtlantisSoCState { /*< private >*/ @@ -41,6 +43,7 @@ struct TTAtlantisSoCState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + TTAtlantisPRCMState prcm[TT_ATL_NUM_PRCM]; uint32_t num_harts; char *cpu_type; @@ -81,6 +84,25 @@ enum { TT_ATL_SAPLIC, TT_ATL_SIMSIC, TT_ATL_UART1, + TT_ATL_PRCM_RCPU, + TT_ATL_PRCM_HSIO, + TT_ATL_PRCM_PCIE, + TT_ATL_PRCM_MM, +}; + +/* + * RCPU PRCM Clock IDs, sourced from linux dt-bindings + * include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h + */ +enum { + TT_ATL_CLK_RCPU_PLL = 0, + TT_ATL_CLK_RCPU_ROOT = 1, + TT_ATL_CLK_NOC_PLL = 25, + TT_ATL_CLK_NOCC_CLK = 26, + TT_ATL_CLK_HSIO_PLL = 54, + TT_ATL_CLK_PCIE_PLL = 55, + TT_ATL_CLK_MM_PLL0 = 56, + TT_ATL_CLK_MM_PLL1 = 57, }; #endif diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..10ae3c2850 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -27,6 +27,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/riscv_aclint.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" #include "system/system.h" #include "system/device_tree.h" @@ -58,12 +59,16 @@ static const MemMapEntry tt_atlantis_memmap[] = { [TT_ATL_ACLINT] = { 0xa2180000, 0x10000 }, [TT_ATL_SIMSIC] = { 0xa4000000, 0x200000 }, [TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 }, + [TT_ATL_PRCM_RCPU] = { 0xd0000000, 0x10000 }, [TT_ATL_I2C0] = { 0xd4040000, 0x10000 }, [TT_ATL_I2C1] = { 0xd4050000, 0x10000 }, [TT_ATL_I2C2] = { 0xd4060000, 0x10000 }, [TT_ATL_I2C3] = { 0xd4070000, 0x10000 }, [TT_ATL_I2C4] = { 0xd4080000, 0x10000 }, [TT_ATL_UART1] = { 0xd4110000, 0x10000 }, + [TT_ATL_PRCM_PCIE] = { 0xd8000000, 0x100 }, + [TT_ATL_PRCM_MM] = { 0xdc000000, 0x1000 }, + [TT_ATL_PRCM_HSIO] = { 0xe00c0000, 0x510 }, [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 }, [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 }, }; @@ -327,11 +332,34 @@ static void create_fdt_i2c_device(void *fdt, TTAtlantisSoCState *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } +static char *create_fdt_prcm(void *fdt, const MemMapEntry *mem, + const char *prcm_name) +{ + hwaddr base = mem->base; + hwaddr size = mem->size; + char *name = g_strdup_printf("/soc/clock-controller@%" PRIx64, + base); + g_autofree char *compatible = + g_strdup_printf("tenstorrent,atlantis-prcm-%s", prcm_name); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", compatible); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, base, 2, size); + qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "#reset-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "phandle", next_phandle()); + + return name; +} + static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle = next_phandle(); uint32_t imsic_s_phandle = next_phandle(); uint32_t periph_clk_phandle = next_phandle(); + uint32_t osc_24m_phandle = next_phandle(); + uint32_t prcm_rcpu_phandle; + g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); @@ -348,6 +376,30 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) aplic_s_phandle); create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); + create_fdt_clk(fdt, "osc-24m", 24000000, osc_24m_phandle); + + rcpu_name = create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_RCPU], "rcpu"); + prcm_rcpu_phandle = qemu_fdt_get_phandle(fdt, rcpu_name); + qemu_fdt_setprop_cells(fdt, rcpu_name, "clocks", osc_24m_phandle); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clocks", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_ROOT, + prcm_rcpu_phandle, TT_ATL_CLK_NOCC_CLK); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clock-parents", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_PLL, + prcm_rcpu_phandle, TT_ATL_CLK_NOC_PLL); + + hsio_name = create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_HSIO], "hsio"); + qemu_fdt_setprop_cells(fdt, hsio_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_HSIO_PLL); + + pcie_name = create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_PCIE], "pcie"); + qemu_fdt_setprop_cells(fdt, pcie_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_PCIE_PLL); + + mm_name = create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_MM], "mm"); + qemu_fdt_setprop_cells(fdt, mm_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL0, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL1); for (int i = 0; i < TT_ATL_NUM_I2C; i++) { create_fdt_i2c(fdt, @@ -491,6 +543,19 @@ static void tt_atlantis_soc_init(Object *obj) object_initialize_child(obj, "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "prcm-rcpu", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU], + TYPE_TT_ATLANTIS_PRCM_RCPU); + object_initialize_child(obj, "prcm-hsio", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO], + TYPE_TT_ATLANTIS_PRCM_HSIO); + object_initialize_child(obj, "prcm-pcie", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE], + TYPE_TT_ATLANTIS_PRCM_PCIE); + object_initialize_child(obj, "prcm-mm", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM], + TYPE_TT_ATLANTIS_PRCM_MM); + for (int i = 0; i < TT_ATL_NUM_I2C; i++) { object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_DESIGNWARE_I2C); @@ -587,6 +652,44 @@ static void tt_atlantis_soc_realize(DeviceState *dev, Error **errp) serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); + + /* 4 PRCM blocks */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_RCPU].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_HSIO].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_PCIE].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_MM].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), 0)); + /* * Atlantis contains a DesignWare uart while the QEMU machine * uses the serial_mm model with the base ns16550 register set. @@ -654,6 +757,7 @@ static void tt_atlantis_machine_init(MachineState *machine) OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ram), &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); /* I2C peripherals: qemu specific */ -- 2.55.0
