On 08.10.2026 06:51, Zephyr Li wrote:
Since commit cfc96df65e01, riscv_pmu_ctr_get_fixed_counters_val() returns the complete 64-bit fixed-counter value. The RV32 counter access paths, however, still perform parts of the offset calculation on separately extracted 32-bit halves.In particular, riscv_pmu_write_ctrh() deposits the low 32 bits of the complete fixed-counter value into the high half of mhpmcounter_prev. riscv_pmu_read_ctr() also subtracts a 32-bit half of the previous value from the complete 64-bit fixed-counter value. Consequently, writes to mcycleh can be lost and carries between the low and high halves are not handled correctly. Keep the fixed-counter offset calculation entirely in 64 bits. Before a running counter is partially written, materialize its current architectural value and reset the fixed-counter baseline. On reads, calculate the complete 64-bit counter value before extracting the half requested by RV32. Register RV32 system TCG tests with the Meson build. Add a test for high-half writes, low-to-high carry, and preserving the carried high half across a subsequent low-half write. Fixes: cfc96df65e01 ("target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4219 Signed-off-by: Zephyr Li <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Chao Liu <[email protected]>
FWIW, I'm _not_ picking this one up for the stable series. It is only applicable for 11.1.x branch (not to 10.0.x LTS branch), but due to the tests and changes in there after 11.1 were released, it becomes a bit more difficult than I'd like. Besides, RV32 is significantly less common than RV64 - in particular, debian does not ship the riscv32 cross-compilers which were used in the newly added tests, - so I can't even verify it easily. Hopefully it's okay :) Thanks, /mjt
