On Fri, 2026-10-16 at 16:23 -0700, Pierrick Bouvier wrote: > List of helpers: > - fadd_s > - fsub_s > - fdiv_s > - fsqrt_s > - fadd_d > - fsub_d > - fdiv_d > - fsqrt_d > - crc32 > - crc32c > - raise_exception > - wfi
Why not just prefix all helpers? Alistair > > Reviewed-by: Daniel Henrique Barboza > <[email protected]> > Signed-off-by: Pierrick Bouvier <[email protected]> > --- > target/riscv/helper.h | 24 +++++++++-------- > -- > target/riscv/tcg/bitmanip_helper.c | 4 ++-- > target/riscv/tcg/fpu_helper.c | 16 ++++++------- > .../tcg/insn_trans/trans_privileged.c.inc | 2 +- > target/riscv/tcg/insn_trans/trans_rvd.c.inc | 8 +++---- > target/riscv/tcg/insn_trans/trans_rvf.c.inc | 8 +++---- > target/riscv/tcg/insn_trans/trans_rvi.c.inc | 4 ++-- > .../tcg/insn_trans/trans_rvzicfiss.c.inc | 2 +- > target/riscv/tcg/insn_trans/trans_xlrbr.c.inc | 4 ++-- > target/riscv/tcg/op_helper.c | 4 ++-- > target/riscv/tcg/translate.c | 4 ++-- > 11 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 372f1049726..6aae192112a 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1,5 +1,5 @@ > /* Exceptions */ > -DEF_HELPER_2(raise_exception, noreturn, env, i32) > +DEF_HELPER_2(riscv_raise_exception, noreturn, env, i32) > > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, > i32) > @@ -20,15 +20,15 @@ DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, > i64, env, i64, i64, i64) > DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, > i64) > > /* Floating Point - Single Precision */ > -DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > -DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(riscv_fadd_s, TCG_CALL_NO_RWG, i64, env, i64, > i64) > +DEF_HELPER_FLAGS_3(riscv_fsub_s, TCG_CALL_NO_RWG, i64, env, i64, > i64) > DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > -DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(riscv_fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, > i64) > DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fminm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fmaxm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) > -DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) > +DEF_HELPER_FLAGS_2(riscv_fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) > DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64) > DEF_HELPER_FLAGS_3(fleq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) > DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64) > @@ -47,17 +47,17 @@ DEF_HELPER_FLAGS_2(fround_s, TCG_CALL_NO_RWG_SE, > i64, env, i64) > DEF_HELPER_FLAGS_2(froundnx_s, TCG_CALL_NO_RWG_SE, i64, env, i64) > > /* Floating Point - Double Precision */ > -DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > -DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(riscv_fadd_d, TCG_CALL_NO_RWG, i64, env, i64, > i64) > +DEF_HELPER_FLAGS_3(riscv_fsub_d, TCG_CALL_NO_RWG, i64, env, i64, > i64) > DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > -DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(riscv_fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, > i64) > DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fminm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_3(fmaxm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) > DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) > DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) > -DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) > +DEF_HELPER_FLAGS_2(riscv_fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) > DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64) > DEF_HELPER_FLAGS_3(fleq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) > DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64) > @@ -83,8 +83,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, > tl) > DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) > DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) > DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) > -DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) > -DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) > +DEF_HELPER_FLAGS_2(riscv_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) > +DEF_HELPER_FLAGS_2(riscv_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) > > /* Floating Point - Half Precision */ > DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) > @@ -135,7 +135,7 @@ DEF_HELPER_1(mret, tl, env) > DEF_HELPER_1(dret, tl, env) > DEF_HELPER_1(mnret, tl, env) > DEF_HELPER_1(ctr_clear, void, env) > -DEF_HELPER_1(wfi, void, env) > +DEF_HELPER_1(riscv_wfi, void, env) > DEF_HELPER_1(wrs_nto, void, env) > DEF_HELPER_1(tlb_flush, void, env) > DEF_HELPER_1(tlb_flush_all, void, env) > diff --git a/target/riscv/tcg/bitmanip_helper.c > b/target/riscv/tcg/bitmanip_helper.c > index d8d94bca7ba..5af3efe194d 100644 > --- a/target/riscv/tcg/bitmanip_helper.c > +++ b/target/riscv/tcg/bitmanip_helper.c > @@ -117,7 +117,7 @@ target_ulong HELPER(xperm8)(target_ulong rs1, > target_ulong rs2) > return do_xperm(rs1, rs2, 3); > } > > -target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) > +target_ulong HELPER(riscv_crc32)(target_ulong rs1, target_ulong sz) > { > for (target_ulong i = 0; i < sz; i++) { > rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8); > @@ -126,7 +126,7 @@ target_ulong HELPER(crc32)(target_ulong rs1, > target_ulong sz) > return rs1; > } > > -target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz) > +target_ulong HELPER(riscv_crc32c)(target_ulong rs1, target_ulong sz) > { > for (target_ulong i = 0; i < sz; i++) { > rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8); > diff --git a/target/riscv/tcg/fpu_helper.c > b/target/riscv/tcg/fpu_helper.c > index db1475271b6..85fc419eb95 100644 > --- a/target/riscv/tcg/fpu_helper.c > +++ b/target/riscv/tcg/fpu_helper.c > @@ -230,14 +230,14 @@ uint64_t helper_fnmadd_h(CPURISCVState *env, > uint64_t frs1, uint64_t frs2, > float_muladd_negate_c | > float_muladd_negate_product); > } > > -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t > rs2) > +uint64_t helper_riscv_fadd_s(CPURISCVState *env, uint64_t rs1, > uint64_t rs2) > { > float32 frs1 = check_nanbox_s(env, rs1); > float32 frs2 = check_nanbox_s(env, rs2); > return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); > } > > -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t > rs2) > +uint64_t helper_riscv_fsub_s(CPURISCVState *env, uint64_t rs1, > uint64_t rs2) > { > float32 frs1 = check_nanbox_s(env, rs1); > float32 frs2 = check_nanbox_s(env, rs2); > @@ -251,7 +251,7 @@ uint64_t helper_fmul_s(CPURISCVState *env, > uint64_t rs1, uint64_t rs2) > return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); > } > > -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t > rs2) > +uint64_t helper_riscv_fdiv_s(CPURISCVState *env, uint64_t rs1, > uint64_t rs2) > { > float32 frs1 = check_nanbox_s(env, rs1); > float32 frs2 = check_nanbox_s(env, rs2); > @@ -292,7 +292,7 @@ uint64_t helper_fmaxm_s(CPURISCVState *env, > uint64_t rs1, uint64_t rs2) > return nanbox_s(env, ret); > } > > -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) > +uint64_t helper_riscv_fsqrt_s(CPURISCVState *env, uint64_t rs1) > { > float32 frs1 = check_nanbox_s(env, rs1); > return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); > @@ -434,12 +434,12 @@ uint64_t helper_froundnx_s(CPURISCVState *env, > uint64_t rs1) > return nanbox_s(env, frs1); > } > > -uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t > frs2) > +uint64_t helper_riscv_fadd_d(CPURISCVState *env, uint64_t frs1, > uint64_t frs2) > { > return float64_add(frs1, frs2, &env->fp_status); > } > > -uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t > frs2) > +uint64_t helper_riscv_fsub_d(CPURISCVState *env, uint64_t frs1, > uint64_t frs2) > { > return float64_sub(frs1, frs2, &env->fp_status); > } > @@ -449,7 +449,7 @@ uint64_t helper_fmul_d(CPURISCVState *env, > uint64_t frs1, uint64_t frs2) > return float64_mul(frs1, frs2, &env->fp_status); > } > > -uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t > frs2) > +uint64_t helper_riscv_fdiv_d(CPURISCVState *env, uint64_t frs1, > uint64_t frs2) > { > return float64_div(frs1, frs2, &env->fp_status); > } > @@ -489,7 +489,7 @@ uint64_t helper_fcvt_d_s(CPURISCVState *env, > uint64_t rs1) > return float32_to_float64(frs1, &env->fp_status); > } > > -uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) > +uint64_t helper_riscv_fsqrt_d(CPURISCVState *env, uint64_t frs1) > { > return float64_sqrt(frs1, &env->fp_status); > } > diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc > b/target/riscv/tcg/insn_trans/trans_privileged.c.inc > index e22df6fbe71..4f18b6c3fa4 100644 > --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc > @@ -168,7 +168,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi > *a) > #ifndef CONFIG_USER_ONLY > decode_save_opc(ctx, 0); > gen_update_pc(ctx, ctx->cur_insn_len); > - gen_helper_wfi(tcg_env); > + gen_helper_riscv_wfi(tcg_env); > ctx->base.is_jmp = DISAS_NORETURN; > return true; > #else > diff --git a/target/riscv/tcg/insn_trans/trans_rvd.c.inc > b/target/riscv/tcg/insn_trans/trans_rvd.c.inc > index 1be2bee9465..596a4ad888e 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvd.c.inc > @@ -194,7 +194,7 @@ static bool trans_fadd_d(DisasContext *ctx, > arg_fadd_d *a) > TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fadd_d(dest, tcg_env, src1, src2); > + gen_helper_riscv_fadd_d(dest, tcg_env, src1, src2); > gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -211,7 +211,7 @@ static bool trans_fsub_d(DisasContext *ctx, > arg_fsub_d *a) > TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fsub_d(dest, tcg_env, src1, src2); > + gen_helper_riscv_fsub_d(dest, tcg_env, src1, src2); > gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -245,7 +245,7 @@ static bool trans_fdiv_d(DisasContext *ctx, > arg_fdiv_d *a) > TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fdiv_d(dest, tcg_env, src1, src2); > + gen_helper_riscv_fdiv_d(dest, tcg_env, src1, src2); > gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -261,7 +261,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, > arg_fsqrt_d *a) > TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fsqrt_d(dest, tcg_env, src1); > + gen_helper_riscv_fsqrt_d(dest, tcg_env, src1); > gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc > b/target/riscv/tcg/insn_trans/trans_rvf.c.inc > index 636dec1664d..551c9b39861 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc > @@ -178,7 +178,7 @@ static bool trans_fadd_s(DisasContext *ctx, > arg_fadd_s *a) > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fadd_s(dest, tcg_env, src1, src2); > + gen_helper_riscv_fadd_s(dest, tcg_env, src1, src2); > gen_set_fpr_hs(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -194,7 +194,7 @@ static bool trans_fsub_s(DisasContext *ctx, > arg_fsub_s *a) > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fsub_s(dest, tcg_env, src1, src2); > + gen_helper_riscv_fsub_s(dest, tcg_env, src1, src2); > gen_set_fpr_hs(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -226,7 +226,7 @@ static bool trans_fdiv_s(DisasContext *ctx, > arg_fdiv_s *a) > TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); > > gen_set_rm(ctx, a->rm); > - gen_helper_fdiv_s(dest, tcg_env, src1, src2); > + gen_helper_riscv_fdiv_s(dest, tcg_env, src1, src2); > gen_set_fpr_hs(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > @@ -241,7 +241,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, > arg_fsqrt_s *a) > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fsqrt_s(dest, tcg_env, src1); > + gen_helper_riscv_fsqrt_s(dest, tcg_env, src1); > gen_set_fpr_hs(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc > b/target/riscv/tcg/insn_trans/trans_rvi.c.inc > index cc1b5dbbadc..8d63efe09b5 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc > @@ -55,7 +55,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad > *a) > */ > > tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > tcg_env, offsetof(CPURISCVState, > sw_check_code)); > - gen_helper_raise_exception(tcg_env, > + gen_helper_riscv_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > return true; > } > @@ -68,7 +68,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad > *a) > tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); > > tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > tcg_env, offsetof(CPURISCVState, > sw_check_code)); > - gen_helper_raise_exception(tcg_env, > + gen_helper_riscv_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > gen_set_label(skip); > } > diff --git a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc > b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc > index d47a9f9c7d2..0556f37805a 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc > @@ -43,7 +43,7 @@ static bool trans_sspopchk(DisasContext *ctx, > arg_sspopchk *a) > tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); > tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL), > tcg_env, offsetof(CPURISCVState, > sw_check_code)); > - gen_helper_raise_exception(tcg_env, > + gen_helper_riscv_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > gen_set_label(skip); > tcg_gen_addi_tl(addr, addr, tmp); > diff --git a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc > b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc > index 01da2b6ce1d..795231f0839 100644 > --- a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc > @@ -29,11 +29,11 @@ static bool gen_crc(DisasContext *ctx, arg_r2 *a, > #define TRANS_CRC32(NAME, SIZE) \ > static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \ > { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \ > - return gen_crc(ctx, a, gen_helper_crc32, > tcg_constant_tl(SIZE)); } > + return gen_crc(ctx, a, gen_helper_riscv_crc32, > tcg_constant_tl(SIZE)); } > #define TRANS_CRC32C(NAME, SIZE) \ > static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \ > { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \ > - return gen_crc(ctx, a, gen_helper_crc32c, > tcg_constant_tl(SIZE)); } > + return gen_crc(ctx, a, gen_helper_riscv_crc32c, > tcg_constant_tl(SIZE)); } > > TRANS_CRC32(b, 1); > TRANS_CRC32(h, 2); > diff --git a/target/riscv/tcg/op_helper.c > b/target/riscv/tcg/op_helper.c > index b8b3e43ccd5..3df01016dfa 100644 > --- a/target/riscv/tcg/op_helper.c > +++ b/target/riscv/tcg/op_helper.c > @@ -48,7 +48,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState > *env, > cpu_loop_exit_restore(cs, pc); > } > > -void helper_raise_exception(CPURISCVState *env, uint32_t exception) > +void helper_riscv_raise_exception(CPURISCVState *env, uint32_t > exception) > { > #ifndef CONFIG_USER_ONLY > riscv_pmu_decr_instret(env); > @@ -625,7 +625,7 @@ void helper_ctr_clear(CPURISCVState *env) > riscv_ctr_clear(env); > } > > -void helper_wfi(CPURISCVState *env) > +void helper_riscv_wfi(CPURISCVState *env) > { > CPUState *cs = env_cpu(env); > bool rvs = riscv_has_ext(env, RVS); > diff --git a/target/riscv/tcg/translate.c > b/target/riscv/tcg/translate.c > index ede9c2563f7..2ffbf26bb19 100644 > --- a/target/riscv/tcg/translate.c > +++ b/target/riscv/tcg/translate.c > @@ -259,7 +259,7 @@ static void gen_update_pc(DisasContext *ctx, > target_long diff) > static void generate_exception(DisasContext *ctx, RISCVException > excp) > { > gen_update_pc(ctx, 0); > - gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); > + gen_helper_riscv_raise_exception(tcg_env, > tcg_constant_i32(excp)); > ctx->base.is_jmp = DISAS_NORETURN; > } > > @@ -1407,7 +1407,7 @@ static void > riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, > link); > > tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > tcg_env, offsetof(CPURISCVState, > sw_check_code)); > - gen_helper_raise_exception(tcg_env, > + gen_helper_riscv_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > tcg_ctx->emit_before_op = NULL; > ctx->base.is_jmp = DISAS_NORETURN;
