[PATCH 2/2] target/hexagon: reset implicit USR write state

[Brian Cain]

implicit_usr_write is per-packet DC state. It was not cleared before
analyzing the next packet. Reset it together with the other per-packet
state.

When running qfloat_v81 ubsan reported:

    target/hexagon/translate.c:725:32: runtime error: load of value 192,
    which is not a valid value for type '_Bool'
    target/hexagon/translate.c:874:12: runtime error: load of value 192,
    which is not a valid value for type '_Bool'

Fixes: 3e98496691ed ("Hexagon (target/hexagon) Implicit writes to USR don't 
force packet commit")
Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
 target/hexagon/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 2c18f5eebff..a4c5e043c72 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -569,6 +569,7 @@ static void clear_pkt_ctx(DisasContext *ctx)
     ctx->reg_log_idx = 0;
     bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
     bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
+    ctx->implicit_usr_write = false;
 #ifndef CONFIG_USER_ONLY
     ctx->greg_log_idx = 0;
     bitmap_zero(ctx->gregs_written, NUM_GREGS);
-- 
2.34.1