On Thu, Oct 15, 2026 at 12:19:53PM +0530, Sunil V L wrote: > Hi all, > > This series adds ACPI Processor Properties Topology Table (PPTT) support to > the RISC-V virt machine. PPTT allows the guest to discover the processor and > cache topology exposed by the machine, which is useful for making better > scheduling and cache-management decisions.
Thanks for picking up PPTT support. I can now rebase the RQSC support [1] on this series. However, RQSC actually needs PPTT revision 3, because it adds cache IDs to the PPTT. The RQSC table references a capacity controller's cache by the PPTT cache ID. In Linux, find_acpi_cache_level_from_id() and acpi_pptt_get_cpumask_from_cache_id() return -ENOENT if PPTT rev < 3. There is a new MPAM series by Jinjie Ruan which contains the patch "[PATCH 04/37] hw/acpi: Build PPTT rev 3 with cache IDs for MPAM cross-references" [2]. It bumps build_pptt() to revision 3 and gives every cache node an ID. I could just base the RQSC series on this PPTT series and that patch 03/37. But maybe there is a better way to coordinate adding PPTT v3? Thanks, Drew [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/
