在 2026/10/21 8:39, Daniel Henrique Barboza 写道:
> Hi Drew!
>
> On 10/20/2026 7:29 PM, Drew Fustini wrote:
>> On Thu, Oct 15, 2026 at 12:19:53PM +0530, Sunil V L wrote:
>>> Hi all,
>>>
>>> This series adds ACPI Processor Properties Topology Table (PPTT)
>>> support to
>>> the RISC-V virt machine. PPTT allows the guest to discover the
>>> processor and
>>> cache topology exposed by the machine, which is useful for making better
>>> scheduling and cache-management decisions.
>>
>> Thanks for picking up PPTT support. I can now rebase the RQSC support
>> [1] on this series.
>>
>> However, RQSC actually needs PPTT revision 3, because it adds cache IDs
>> to the PPTT. The RQSC table references a capacity controller's cache by
>> the PPTT cache ID. In Linux, find_acpi_cache_level_from_id() and
>> acpi_pptt_get_cpumask_from_cache_id() return -ENOENT if PPTT rev < 3.
>>
>> There is a new MPAM series by Jinjie Ruan which contains the patch
>> "[PATCH 04/37] hw/acpi: Build PPTT rev 3 with cache IDs for MPAM
>> cross-references" [2]. It bumps build_pptt() to revision 3 and gives
>> every cache node an ID.
>>
>> I could just base the RQSC series on this PPTT series and that patch
>> 03/37. But maybe there is a better way to coordinate adding PPTT v3?
>
> This PPTT support is acked and I believe we'll queue it in riscv-to-
> apply.next
> shortly.
>
> As for the PPTT rev3 patch in the "Add Arm MPAM emulation", my
> suggestion is
> to put that on top of your series (i.e. your series will contain that
> patch).
> That ARM series has 37 patches and might take awhile to go through, and
> your
> work relies only on patch 04 ... which happens to be an arch agnostic
> patch.
> I believe it's fine for us to push it via the riscv queue.
>
> I see that the author from the ARM series is CCed here. Jinjie Ruan,
> are you
> okay with us pushing your patch via the RISC-V tree? It'll unblock
> Drew's work
> and you'll have one less patch to worry about in your ARM MPAM work.
Hi Daniel,
I'm fine to do so.
>
>
> Thanks,
> Daniel
>
>
>
>
>
>>
>> Thanks,
>> Drew
>>
>> [1] https://lore.kernel.org/all/20260202-riscv-rqsc-v1-0-
>> [email protected]/
>> [2] https://lore.kernel.org/all/
>> [email protected]/
>
--
Best regards,
Jinjie
