From: Strahinja Jankovic <[email protected]> The original Allwinner GPIO implementation assumed pin had to be configured as input (CFG 0x0) in order to be able to handle interrupts on interrupt-capable pins. However, libgpiod configures those pins in EINT mode (CFG 0x06) when gpiomon is used, so this patch fixes interrupt path to expect pin configuration to be set to EINT.
Also update interrupt handling tests for the correct functionality. Signed-off-by: Strahinja Jankovic <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]> --- include/hw/gpio/allwinner-gpio-regs.h | 5 +---- hw/gpio/allwinner-gpio.c | 19 ++++++++++++----- tests/qtest/allwinner-gpio-test.c | 30 +++++++++++++-------------- 3 files changed, 30 insertions(+), 24 deletions(-) diff --git a/include/hw/gpio/allwinner-gpio-regs.h b/include/hw/gpio/allwinner-gpio-regs.h index a435b87ec49..5e969c23f62 100644 --- a/include/hw/gpio/allwinner-gpio-regs.h +++ b/include/hw/gpio/allwinner-gpio-regs.h @@ -73,9 +73,6 @@ static const AWPortResetVals aw_gpio_port_reset[] = { #define DEFAULT_DRV_MASK 0xffffffff #define DEFAULT_PUL_MASK 0xffffffff -#define CFG_INPUT_MASK 0x0 -#define CFG_OUTPUT_MASK 0x1 -#define CFG_IO_MASK 0x1 #define CFG_PIN_STRIDE 4 #define CFG_PINS_PER_REG (AW_GPIO_PIN_COUNT / CFG_PIN_STRIDE) @@ -172,7 +169,7 @@ typedef enum AWGPIOLevel { typedef enum AWGPIOCfg { AW_GPIO_CFG_IN = 0, AW_GPIO_CFG_OUT = 1, - AW_GPIO_CFG_FUN = 2, + AW_GPIO_CFG_EINT = 6, } AWGPIOCfg; typedef enum AWGPIOIrqCfg { diff --git a/hw/gpio/allwinner-gpio.c b/hw/gpio/allwinner-gpio.c index e3bda7cb762..19176e7c56f 100644 --- a/hw/gpio/allwinner-gpio.c +++ b/hw/gpio/allwinner-gpio.c @@ -114,7 +114,7 @@ static inline bool gpio_is_output(AWPortMap *port, uint32_t pin) uint32_t cfg_n = pin / CFG_PINS_PER_REG; uint32_t pin_shift = (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) == - CFG_OUTPUT_MASK); + AW_GPIO_CFG_OUT); } static inline bool gpio_is_input(AWPortMap *port, uint32_t pin) @@ -122,7 +122,15 @@ static inline bool gpio_is_input(AWPortMap *port, uint32_t pin) uint32_t cfg_n = pin / CFG_PINS_PER_REG; uint32_t pin_shift = (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) == - CFG_INPUT_MASK); + AW_GPIO_CFG_IN); +} + +static inline bool gpio_is_eint(AWPortMap *port, uint32_t pin) +{ + uint32_t cfg_n = pin / CFG_PINS_PER_REG; + uint32_t pin_shift = (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; + return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) == + AW_GPIO_CFG_EINT); } static inline int int_ctl_cfg(AWGPIOState *s, int irq_line) @@ -155,8 +163,8 @@ static void allwinner_gpio_set_int_line(AWGPIOState *s, int port, return; } - /* if this signal isn't configured as an input signal, nothing to do */ - if (!gpio_is_input(&o->ports[port], line)) { + /* if this signal isn't configured as an EINT, nothing to do */ + if (!gpio_is_eint(&o->ports[port], line)) { return; } @@ -225,7 +233,8 @@ static void allwinner_gpio_set(void *opaque, int port, int line, int level) AWPortsOverlay *o = (AWPortsOverlay *)s->regs; AWGPIOLevel aw_level = level ? AW_GPIO_LEVEL_HIGH : AW_GPIO_LEVEL_LOW; - if (gpio_is_input(&o->ports[port], line)) { + if (gpio_is_input(&o->ports[port], line) || + gpio_is_eint(&o->ports[port], line)) { trace_allwinner_gpio_set(portname(port), line, aw_level); diff --git a/tests/qtest/allwinner-gpio-test.c b/tests/qtest/allwinner-gpio-test.c index c048f0f88b9..7ad89f6e0a3 100644 --- a/tests/qtest/allwinner-gpio-test.c +++ b/tests/qtest/allwinner-gpio-test.c @@ -251,9 +251,9 @@ static void test_irq_pin_rising(const void *data) qtest_irq_intercept_in(s, "/machine/soc"); - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); @@ -296,9 +296,9 @@ static void test_irq_pin_falling(const void *data) qtest_irq_intercept_in(s, "/machine/soc"); - /* Configure as input and set pin high */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin high */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_HIGH); @@ -341,9 +341,9 @@ static void test_irq_pin_high_level(const void *data) qtest_irq_intercept_in(s, "/machine/soc"); - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); @@ -394,9 +394,9 @@ static void test_irq_pin_low_level(const void *data) qtest_irq_intercept_in(s, "/machine/soc"); - /* Configure as input and set pin high */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin high */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_HIGH); @@ -447,9 +447,9 @@ static void test_irq_pin_both_edge(const void *data) qtest_irq_intercept_in(s, "/machine/soc"); - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); -- 2.43.0
