On 2026-10-10 19:46, Aurelien Jarno wrote:
> For logical vector operations (in the case of the RISC-V backend that
> corresponds to and_vec, or_vec and xor_vec), VECE is unused. However,
> tcg_target_const_match() always treat it as an element size to extract
> the corresponding constant element from the whole constant.
>
> This causes the following aarch64 instruction
> bic v4.8h, #0xf0
> to be translated into the following op:
> ...
> and_vec v128,e8,tmp5,tmp4,v128$0xff0fff0fff0fff0f
> ...
> which is then translated to the following RISC-V instruction:
> vand.vi v1,v1,15
>
> Fix that by, when VECE is 0 aka MO_8, only extracting the element if the
> it can actually be represented as a duplicated constant.
>
> Fixes: 5a63f5998791 ("tcg/riscv: Add support for basic vector opcodes")
> Signed-off-by: Aurelien Jarno <[email protected]>
> ---
> tcg/riscv64/tcg-target.c.inc | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> Changes v1 -> v2:
> - Use dup_const() instead of open coding the constant duplication.
>
> diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc
> index 14a397117a..1262b71a62 100644
> --- a/tcg/riscv64/tcg-target.c.inc
> +++ b/tcg/riscv64/tcg-target.c.inc
> @@ -392,8 +392,15 @@ static bool tcg_target_const_match(int64_t val, int ct,
> return 1;
> }
> if (type >= TCG_TYPE_V64) {
> - /* Val is replicated by VECE; extract the highest element. */
> - val >>= (-8 << vece) & 63;
> + /*
> + * For vector logical operations, VECE is unused and equals to 0, so
> + * we need to check that the constant can properly be represented
> after
> + * replication.
> + */
> + if ((vece != MO_8) || (val == dup_const(vece, val))) {
> + /* Val is replicated by VECE; extract the highest element. */
> + val >>= (-8 << vece) & 63;
> + }
> }
> /*
> * Sign extended from 12 bits: [-0x800, 0x7ff].
Gentle ping about this patch. Are there more things to fix?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://aurel32.net
