Zalasr loads and stores unconditionally request MO_ALIGN. Adding MO_ATOM_WITHIN16 therefore does not relax their natural alignment requirement when Zama16b is enabled.
Select MO_ATOM_WITHIN16 when Zama16b is enabled and retain MO_ALIGN otherwise. Preserve the existing acquire and release barriers. Signed-off-by: GavinQin <[email protected]> --- target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc b/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc index 79b0b2c63b..5bbd06a346 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc @@ -29,8 +29,12 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop) return false; } - memop |= MO_ALIGN | ctx->mo_endianness; - memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; + memop |= ctx->mo_endianness; + if (ctx->cfg_ptr->ext_zama16b) { + memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ALIGN; + } tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -79,8 +83,12 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop) return false; } - memop |= MO_ALIGN | ctx->mo_endianness; - memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; + memop |= ctx->mo_endianness; + if (ctx->cfg_ptr->ext_zama16b) { + memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ALIGN; + } /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL | bar); -- 2.34.1
