From: Daniel Henrique Barboza <[email protected]> In commit 18645f195789 we removed the capability of MPV/GVA writes by software, claiming that the ISA says that these bits are changed by the implementation (i.e. hardware).
This fact alone can't be interpret as "so software can't change them". The ISA never mentions that, and we shouldn't just assume read/write accesses based on whether hardware updates it or not. M-mode software can do whatever they want, unless clearly stated in the ISA, and that includes mstatus MPV and GVA updates. And in fact existing software is writing to these bits, as reported by Fangyu in [1], and that change ended up causing real problems in the end. Revert "target/riscv/csr.c: do not allow mstatus MPV/GVA writes". This reverts commit 18645f19578955ec5ff2c40cd2c8753d6bc460c2. [1] https://lore.kernel.org/qemu-devel/[email protected]/ Reported-by: Fangyu Yu <[email protected]> Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/tcg/csr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 13675b4a8439..af444e3e6f32 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -2108,6 +2108,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, } if (xl != MXL_RV32 || env->debugger) { + if (riscv_has_ext(env, RVH)) { + mask |= MSTATUS_MPV | MSTATUS_GVA; + } if ((val & MSTATUS64_SXL) != 0) { mask |= MSTATUS64_SXL; val = riscv_write_uxl(env, val, MSTATUS64_SXL); @@ -2150,7 +2153,7 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { uint64_t valh = (uint64_t)val << 32; - uint64_t mask = 0; + uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; if (riscv_cpu_cfg(env)->ext_smdbltrp) { mask |= MSTATUS_MDT; -- 2.55.0
