Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
---
hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 6 ++-
hw/hexagon/sa8775p_cdsp.c | 59 +++++++++++++++++++++++
tests/qtest/l2vic-test.c | 2 +
tests/qtest/qcom-dsp-test.c | 1 +
tests/qtest/qct-qtimer-test.c | 2 +
hw/hexagon/Kconfig | 6 +++
hw/hexagon/meson.build | 1 +
7 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 hw/hexagon/sa8775p_cdsp.c
diff --git a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
index 442cbe3be31..7e2ef42b9e2 100644
--- a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
+++ b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
static const struct hexagon_machine_config SA8775P_cdsp0 = {
+ .ddr_base = 0x80000000,
.cfgbase = 0x24000000 + 0x180000,
.l2tcm_size = 0x00000000,
.l2vic_base = 0x26300000 + 0x90000,
@@ -25,7 +26,7 @@ static const struct hexagon_machine_config SA8775P_cdsp0 = {
.vtcm_base = 0x00002500,
.vtcm_size_kb = 0x00002000,
.l2tag_size = 0x00000400,
- .l2ecomem_size = 0x00000000,
+ .l2ecomem_size = 0x00000400,
.thread_enable_mask = 0x0000003f,
.eccreg_base = 0x0000241f,
.l2line_size = 0x00000080,
@@ -60,5 +61,8 @@ static const struct hexagon_machine_config SA8775P_cdsp0 = {
.consistency_domain = 0x000000e0,
.capacity_domain = 0x00000080,
.axi3_lowaddr = 0x00000000,
+ .coproc2_int8_subcolumns = 0x00000002,
+ .corecfg_present = 0x00000005,
+ .coproc2_fp16_acc_exp = 0x00000007,
},
};
diff --git a/hw/hexagon/sa8775p_cdsp.c b/hw/hexagon/sa8775p_cdsp.c
new file mode 100644
index 00000000000..de44f8f65cc
--- /dev/null
+++ b/hw/hexagon/sa8775p_cdsp.c
@@ -0,0 +1,59 @@
+/*
+ * Models the v73 CDSP0 of the SA8775P.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/core/boards.h"
+#include "hw/hexagon/hexagon.h"
+#include "hw/hexagon/qcom_dsp.h"
+#include "target/hexagon/cpu.h"
+
+#include "machine_cfg_sa8775_cdsp0.h.inc"
+
+#define TYPE_SA8775P_CDSP_MACHINE MACHINE_TYPE_NAME("sa8775p-cdsp")
+
+static const QcomDspRegion sa8775p_cdsp_regions[] = {
+ { "tcsr", 0x01fc0000 },
+ { "hwkm-prng", 0x010da000 },
+ { "gdscr", 0x00151000 },
+ { "pll0", 0x26340000 },
+ { "pll1", 0x26000000 },
+ { "clkctl", 0x26348000 },
+ { "ccswi", 0x26008000 },
+ { "rsc", 0x260a4000 },
+};
+
+static void sa8775p_cdsp_init_devices(MachineState *ms)
+{
+ qcom_dsp_add_regions(ms, sa8775p_cdsp_regions,
+ ARRAY_SIZE(sa8775p_cdsp_regions));
+
+ qcom_soc_add_qup_geni_ports("sa8775p", 0x00b80000, 1, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8775p", 0x00880000, 7, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8775p", 0x00980000, 7, 0x4000);
+ qcom_soc_add_qup_geni_ports("sa8775p", 0x00a80000, 7, 0x4000);
+}
+
+static const QcomDspMachineInfo sa8775p_cdsp_info = {
+ .desc = "SA8775P CDSP0",
+ .cpu_type = HEXAGON_CPU_TYPE_NAME("v73"),
+ .cpus = 6,
+ .rev = v73_rev,
+ .cfg = &SA8775P_cdsp0,
+ .kernel_addr = 0xa0000000,
+ .init_devices = sa8775p_cdsp_init_devices,
+};
+
+static const TypeInfo sa8775p_cdsp_types[] = {
+ {
+ .name = TYPE_SA8775P_CDSP_MACHINE,
+ .parent = TYPE_QCOM_DSP_MACHINE,
+ .class_init = qcom_dsp_class_init,
+ .class_data = &sa8775p_cdsp_info,
+ },
+};
+
+DEFINE_TYPES(sa8775p_cdsp_types)
diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c
index 2e0d7dcb0f1..5d30d18a9fd 100644
--- a/tests/qtest/l2vic-test.c
+++ b/tests/qtest/l2vic-test.c
@@ -12,6 +12,7 @@
#include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
#include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
/* L2VIC register offsets exercised by this test */
#define L2VIC_INT_ENABLEn 0x100 /* Read/Write */
@@ -47,6 +48,7 @@ static const L2VICMachineCfg l2vic_machines[] = {
{ "virt", &v68n_1024 },
{ "V66G_1024", &v66g_1024 },
{ "qcs6490-cdsp", &qcs6490_cdsp },
+ { "sa8775p-cdsp", &SA8775P_cdsp0 },
};
static uint32_t l2vic_read32(uint64_t base, uint32_t offset)
diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c
index 39d6e53bc4e..586e113c181 100644
--- a/tests/qtest/qcom-dsp-test.c
+++ b/tests/qtest/qcom-dsp-test.c
@@ -24,6 +24,7 @@
static const char *const qcom_dsp_machines[] = {
"qcs6490-cdsp",
+ "sa8775p-cdsp",
};
static void test_console(const void *machine)
diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c
index 263751b55bf..b20d4a2bced 100644
--- a/tests/qtest/qct-qtimer-test.c
+++ b/tests/qtest/qct-qtimer-test.c
@@ -13,6 +13,7 @@
#include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
#include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
#define QTIMER_DEFAULT_FREQ_HZ 19200000ULL
@@ -344,6 +345,7 @@ static const QtimerMachineCfg qtimer_machines[] = {
{ "virt", &v68n_1024 },
{ "V66G_1024", &v66g_1024 },
{ "qcs6490-cdsp", &qcs6490_cdsp },
+ { "sa8775p-cdsp", &SA8775P_cdsp0 },
};
static void test_qtimer_on_machine(gconstpointer data)
diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig
index ffc8623691c..bdda7872878 100644
--- a/hw/hexagon/Kconfig
+++ b/hw/hexagon/Kconfig
@@ -36,3 +36,9 @@ config HEX_QCS6490_CDSP
default y
depends on HEX_DSP && FDT
select HEX_QCOM_DSP
+
+config HEX_SA8775P_CDSP
+ bool
+ default y
+ depends on HEX_DSP && FDT
+ select HEX_QCOM_DSP
diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build
index 7145e8a65df..b7496426c9a 100644
--- a/hw/hexagon/meson.build
+++ b/hw/hexagon/meson.build
@@ -8,5 +8,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_BOARD', if_true:
files('hex-board.c'))
hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c'))
hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: files('qcom_dsp.c'))
hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true:
files('qcs6490_cdsp.c'))
+hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true:
files('sa8775p_cdsp.c'))
hw_arch += {'hexagon': hexagon_ss}
--
2.34.1
