Add decode and translation for trap2 and the vallocframe and vdeallocframe instruction forms introduced with v83. Model vector stack overflow as a precise exception and report it to linux-user as SIGSEGV.
Teach the IDEF parser about VSP and vector frame checks. Describe the vallocframe and vdeallocframe instruction semantics in system.idef, and move the vector stack overflow check into a shared TCG generator helper. Reviewed-by: Pierrick Bouvier <[email protected]> Reviewed-by: Marco Liebel <[email protected]> Signed-off-by: Brian Cain <[email protected]> --- target/hexagon/cpu_bits.h | 2 + target/hexagon/gen_tcg.h | 51 +++++++++++++++++++++ target/hexagon/genptr.h | 1 + target/hexagon/hex_regs.h | 2 + target/hexagon/idef-parser/parser-helpers.h | 1 + target/hexagon/translate.h | 1 + linux-user/hexagon/cpu_loop.c | 5 ++ target/hexagon/cpu.c | 2 +- target/hexagon/decode.c | 1 + target/hexagon/genptr.c | 21 +++++++++ target/hexagon/hexswi.c | 24 +++++++++- target/hexagon/iclass.c | 1 + target/hexagon/idef-parser/parser-helpers.c | 14 ++++++ target/hexagon/translate.c | 2 +- target/hexagon/tag_rev_info.c.inc | 10 ++++ target/hexagon/gen_idef_parser_funcs.py | 2 +- target/hexagon/idef-parser/idef-parser.lex | 8 ++++ target/hexagon/idef-parser/idef-parser.y | 9 +++- target/hexagon/imported/encode_pp.def | 5 ++ target/hexagon/imported/system.idef | 8 ++++ 20 files changed, 165 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 7d1bdfcbc71..f5f1349b071 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -41,6 +41,7 @@ enum hex_event { HEX_EVENT_TLB_MISS_RW = 0x6, HEX_EVENT_TRAP0 = 0x8, HEX_EVENT_TRAP1 = 0x9, + HEX_EVENT_TRAP2 = 0xa, HEX_EVENT_FPTRAP = 0xb, HEX_EVENT_DEBUG = 0xc, HEX_EVENT_INT0 = 0x10, @@ -79,6 +80,7 @@ enum hex_cause { HEX_CAUSE_NO_COPROC2_ENABLE = 0x018, HEX_CAUSE_PRIV_USER_NO_GINSN = 0x01a, HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b, + HEX_CAUSE_VECTOR_STACK_OVERFLOW = 0x01c, HEX_CAUSE_REG_WRITE_CONFLICT = 0x01d, HEX_CAUSE_PC_NOT_ALIGNED = 0x01e, HEX_CAUSE_MISALIGNED_LOAD = 0x020, diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 38d8558c97a..ae94127e302 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -531,6 +531,57 @@ do { RsV = RsV; } while (0) #endif +#ifdef CONFIG_USER_ONLY +#define fGEN_TCG_V2_CHECK_AND_WRITE_VSP(VSP) \ + do { \ + TCGLabel *write_vsp = gen_new_label(); \ + tcg_gen_brcond_tl(TCG_COND_GEU, VSP, \ + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); \ + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc); \ + gen_set_label(write_vsp); \ + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], VSP); \ + } while (0) +#else +#define fGEN_TCG_V2_CHECK_AND_WRITE_VSP(VSP) \ + do { \ + TCGLabel *write_vsp = gen_new_label(); \ + TCGv mode = tcg_temp_new(); \ + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], \ + 1 << reg_field_info[SSR_EX].offset); \ + tcg_gen_brcondi_tl(TCG_COND_NE, mode, 0, write_vsp); \ + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], \ + 1 << reg_field_info[SSR_UM].offset); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, mode, 0, write_vsp); \ + tcg_gen_brcond_tl(TCG_COND_GEU, VSP, \ + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); \ + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc); \ + gen_set_label(write_vsp); \ + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], VSP); \ + } while (0) +#endif +#define fGEN_TCG_V2_vallocframe_imm(SHORTCODE) \ + do { \ + TCGv vsp = tcg_temp_new(); \ + tcg_gen_subi_tl(vsp, hex_gpr[HEX_REG_VSP], uiV << 11); \ + fGEN_TCG_V2_CHECK_AND_WRITE_VSP(vsp); \ + } while (0) +#define fGEN_TCG_V2_vallocframe_reg(SHORTCODE) \ + do { \ + TCGv size = tcg_temp_new(); \ + TCGv vsp = tcg_temp_new(); \ + tcg_gen_shli_tl(size, RsV, 11); \ + tcg_gen_sub_tl(vsp, hex_gpr[HEX_REG_VSP], size); \ + fGEN_TCG_V2_CHECK_AND_WRITE_VSP(vsp); \ + } while (0) +#define fGEN_TCG_V2_vdeallocframe_imm(SHORTCODE) \ + tcg_gen_addi_tl(hex_gpr[HEX_REG_VSP], hex_gpr[HEX_REG_VSP], uiV << 11) +#define fGEN_TCG_V2_vdeallocframe_reg(SHORTCODE) \ + do { \ + TCGv size = tcg_temp_new(); \ + tcg_gen_shli_tl(size, RsV, 11); \ + tcg_gen_add_tl(hex_gpr[HEX_REG_VSP], hex_gpr[HEX_REG_VSP], size); \ + } while (0) + /* * allocframe(#uiV) * RxV == r29 diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 7c0e90e93aa..270375251f8 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -69,6 +69,7 @@ typedef enum { void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, HexAtomicOp operation); void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 src); +void gen_vframecheck(DisasContext *ctx, TCGv vsp); void probe_noshuf_load(TCGv va, int s, int mi); void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h index 1f6bf9f88a0..03feca477b6 100644 --- a/target/hexagon/hex_regs.h +++ b/target/hexagon/hex_regs.h @@ -77,6 +77,8 @@ enum { HEX_REG_QEMU_PKT_CNT = 52, HEX_REG_QEMU_INSN_CNT = 53, HEX_REG_QEMU_HVX_CNT = 54, + HEX_REG_VFRAMELIMIT = 60, + HEX_REG_VSP = 61, HEX_REG_UTIMERLO = 62, HEX_REG_UTIMERHI = 63, }; diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h index d3dfcec5690..0c9ddc0727e 100644 --- a/target/hexagon/idef-parser/parser-helpers.h +++ b/target/hexagon/idef-parser/parser-helpers.h @@ -296,6 +296,7 @@ void gen_cancel(Context *c, YYLTYPE *locp); void gen_load_cancel(Context *c, YYLTYPE *locp); void gen_framecheck(Context *c, YYLTYPE *locp, HexValue *addr, HexValue *ea); +void gen_vframecheck(Context *c, YYLTYPE *locp, HexValue *addr); void gen_load(Context *c, YYLTYPE *locp, HexValue *size, HexSignedness signedness, HexValue *ea, HexValue *dst); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 98a5b39dd76..54a44b14c6b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -365,6 +365,7 @@ extern TCGv_i64 hex_llsc_val_i64; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; +void gen_precise_exception(int cause, uint32_t pc); #ifdef CONFIG_USER_ONLY #define hex_hvx_ptr tcg_env #define HEX_HVX_OFFSET(member) offsetof(CPUHexagonState, hvx_ctx.member) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e6bb3b62a9f..22570a12648 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -48,6 +48,7 @@ void cpu_loop(CPUHexagonState *env) /* just indicate that signals should be handled asap */ break; case HEX_EVENT_TRAP0: + case HEX_EVENT_TRAP2: syscallnum = env->gpr[6]; env->gpr[HEX_REG_PC] += 4; ret = do_syscall(env, @@ -73,6 +74,10 @@ void cpu_loop(CPUHexagonState *env) force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->gpr[HEX_REG_PC]); break; + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_BNDERR, + env->gpr[HEX_REG_PC]); + break; case HEX_CAUSE_PRIV_USER_NO_GINSN: case HEX_CAUSE_PRIV_USER_NO_SINSN: case HEX_CAUSE_INVALID_PACKET: diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e77097befc8..de6d8e3569e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -88,7 +88,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", - "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", + "c24", "c25", "c26", "c27", "vframelimit", "vsp", "c30", "c31", }; #ifndef CONFIG_USER_ONLY diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 89e961331ff..a28bf9ce9fe 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -186,6 +186,7 @@ static bool decode_opcode_can_jump(int opcode) (GET_ATTRIB(opcode, A_CALL)) || (opcode == J2_trap0) || (opcode == J2_trap1) || + (opcode == J2_trap2) || (opcode == J2_rte) || (opcode == J2_pause)) { /* Exception to A_JUMP attribute */ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 58c31b05d57..d234f994f46 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -730,6 +730,27 @@ void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 src) MO_LE | MO_64 | MO_ALIGN); } +void gen_vframecheck(DisasContext *ctx, TCGv vsp) +{ + TCGLabel *write_vsp = gen_new_label(); + +#ifndef CONFIG_USER_ONLY + TCGv mode = tcg_temp_new(); + + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], + 1 << reg_field_info[SSR_EX].offset); + tcg_gen_brcondi_tl(TCG_COND_NE, mode, 0, write_vsp); + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], + 1 << reg_field_info[SSR_UM].offset); + tcg_gen_brcondi_tl(TCG_COND_EQ, mode, 0, write_vsp); +#endif + tcg_gen_brcond_tl(TCG_COND_GEU, vsp, + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc); + gen_set_label(write_vsp); + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], vsp); +} + #ifndef CONFIG_HEXAGON_IDEF_PARSER static TCGv gen_slotval(DisasContext *ctx) { diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index 92506c26817..2074f135508 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -366,6 +366,10 @@ static void coredump(CPUHexagonState *env) fprintf(f, "0x%x, Stack limit check error", HEX_CAUSE_STACK_LIMIT); break; + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: + fprintf(f, "0x%x, Vector stack overflow", + HEX_CAUSE_VECTOR_STACK_OVERFLOW); + break; case HEX_CAUSE_FPTRAP_CAUSE_BADFLOAT: fprintf(f, "0x%x, Floating-Point: Execution of Floating-Point " "instruction resulted in exception", @@ -777,6 +781,11 @@ void hexagon_cpu_do_interrupt(CPUState *cs) set_addresses(env, 4, cs->exception_index); break; + case HEX_EVENT_TRAP2: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 4, cs->exception_index); + break; + case HEX_EVENT_TLB_MISS_X: switch (env->cause_code) { case HEX_CAUSE_TLBMISSX_CAUSE_NORMAL: @@ -882,6 +891,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) case HEX_CAUSE_NO_COPROC_ENABLE: case HEX_CAUSE_NO_COPROC2_ENABLE: case HEX_CAUSE_UNSUPPORTED_HVX_64B: + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: case HEX_CAUSE_REG_WRITE_CONFLICT: case HEX_CAUSE_VWCTRL_WINDOW_MISS: hexagon_ssr_set_cause(env, env->cause_code); @@ -962,7 +972,19 @@ void register_trap_exception(CPUHexagonState *env, int traptype, int imm, { CPUState *cs = env_cpu(env); - cs->exception_index = (traptype == 0) ? HEX_EVENT_TRAP0 : HEX_EVENT_TRAP1; + switch (traptype) { + case 0: + cs->exception_index = HEX_EVENT_TRAP0; + break; + case 1: + cs->exception_index = HEX_EVENT_TRAP1; + break; + case 2: + cs->exception_index = HEX_EVENT_TRAP2; + break; + default: + g_assert_not_reached(); + } ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); env->cause_code = imm; diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c index c3f8523b27d..00b8108a8fb 100644 --- a/target/hexagon/iclass.c +++ b/target/hexagon/iclass.c @@ -50,6 +50,7 @@ SlotMask find_iclass_slots(Opcode opcode, int itype) } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) { return SLOTS_0; } else if ((opcode == J2_trap0) || + (opcode == J2_trap2) || (opcode == Y2_isync) || (opcode == J2_pause)) { return SLOTS_2; diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c index 14840d98737..8e35ec4dc02 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -25,6 +25,7 @@ #include <string.h> #include <unistd.h> +#include "hex_regs.h" #include "idef-parser.h" #include "parser-helpers.h" #include "idef-parser.tab.h" @@ -1313,6 +1314,11 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value) yyassert(c, locp, reg->type == REGISTER, "reg must be a register!"); value_m = gen_rvalue_truncate(c, locp, &value_m); value_m = rvalue_materialize(c, locp, &value_m); + if (reg->reg.id == HEX_REG_VSP) { + OUT(c, locp, "tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], ", &value_m, + ");\n"); + return; + } OUT(c, locp, "tcg_gen_mov_tl(get_result_gpr(ctx, ", ®->reg.id, "), ", @@ -1740,6 +1746,14 @@ void gen_framecheck(Context *c, YYLTYPE *locp, HexValue *addr, HexValue *ea) OUT(c, locp, "gen_framecheck(ctx, ", &addr_m, ", ", &ea_m, ");\n"); } +void gen_vframecheck(Context *c, YYLTYPE *locp, HexValue *addr) +{ + HexValue addr_m = rvalue_materialize(c, locp, addr); + + addr_m = gen_rvalue_truncate(c, locp, &addr_m); + OUT(c, locp, "gen_vframecheck(ctx, ", &addr_m, ");\n"); +} + void gen_load(Context *c, YYLTYPE *locp, HexValue *width, HexSignedness signedness, HexValue *ea, HexValue *dst) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2f5e9f21098..39ea6172b3e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -136,7 +136,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, return offset; } -static void gen_precise_exception(int cause, uint32_t PC) +void gen_precise_exception(int cause, uint32_t PC) { tcg_gen_movi_i32(hex_cause_code, cause); gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE), diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc index a1b7b50cbf2..c2d4886a846 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -699,6 +699,16 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = { }, [V6_vconv_bf_qf32] = { .introduced = HEX_VER_V81, .removed = HEX_VER_NONE }, + [V2_vallocframe_imm] = { .introduced = HEX_VER_V83, + .removed = HEX_VER_NONE }, + [V2_vallocframe_reg] = { .introduced = HEX_VER_V83, + .removed = HEX_VER_NONE }, + [V2_vdeallocframe_imm] = { .introduced = HEX_VER_V83, + .removed = HEX_VER_NONE }, + [V2_vdeallocframe_reg] = { .introduced = HEX_VER_V83, + .removed = HEX_VER_NONE }, + [J2_trap2] = { .introduced = HEX_VER_V83, .removed = HEX_VER_NONE }, + [Y4_dcfetch_multi] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, [AM_addw_aq] = { .introduced = HEX_VER_V85, .removed = HEX_VER_NONE }, diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py index 7151a4f6713..9293be4c398 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -77,7 +77,7 @@ def main(): if tag in {"S4_vrcrotate_acc", "S4_vrcrotate"}: continue ## Skip trap instructions - if tag in {"J2_trap0", "J2_trap1"}: + if tag in {"J2_trap0", "J2_trap1", "J2_trap2"}: continue ## Skip 128-bit instructions if tag in {"A7_croundd_ri", "A7_croundd_rr"}: diff --git a/target/hexagon/idef-parser/idef-parser.lex b/target/hexagon/idef-parser/idef-parser.lex index cd5958ec904..c2fc10dccce 100644 --- a/target/hexagon/idef-parser/idef-parser.lex +++ b/target/hexagon/idef-parser/idef-parser.lex @@ -161,6 +161,7 @@ STRING_LIT \"(\\.|[^"\\])*\" "fFRAME_SCRAMBLE" | "fFRAME_UNSCRAMBLE" { return FSCR; } "fFRAMECHECK" { return FCHK; } +"fVFRAMECHECK" { return VFCHK; } "Constant_extended" { return CONSTEXT; } "fCL1_"{DIGIT} { return LOCNT; } "fbrev" { return BREV; } @@ -329,6 +330,13 @@ STRING_LIT \"(\\.|[^"\\])*\" yylval->rvalue.bit_width = 32; yylval->rvalue.signedness = UNSIGNED; return REG; } +"VSP" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = HEX_REG_VSP; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.signedness = UNSIGNED; + return REG; } "fREAD_FP()" | "FP" { yylval->rvalue.type = REGISTER; yylval->rvalue.reg.type = GENERAL_PURPOSE; diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y index 3cffafa5b76..b846cf24d01 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -51,7 +51,7 @@ %token IN INAME VAR %token ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS ASL -%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK SXT +%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK VFCHK SXT %token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG %token LOAD_CANCEL STORE_CANCEL CANCEL IDENTITY ROTL INSBITS SETBITS EXTRANGE %token CAST4_8U FAIL CARRY_FROM_ADD ADDSAT64 LSBNEW @@ -398,6 +398,7 @@ assign_statement : lvalue '=' rvalue ; control_statement : frame_check + | vframe_check | cancel_statement | if_statement | for_statement @@ -409,6 +410,12 @@ frame_check : FCHK '(' rvalue ',' rvalue ')' ';' } ; +vframe_check : VFCHK '(' rvalue ',' rvalue ')' ';' + { + gen_vframecheck(c, &@1, &$3); + } + ; + cancel_statement : LOAD_CANCEL { gen_load_cancel(c, &@1); diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def index c590ed4f959..ed1de09a40c 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -409,6 +409,11 @@ DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii 001iiiii") DEF_ENC32(Y2_dcfetchbo, "10010100000sssssPP000iiiiiiiiiii") DEF_ENC32(Y4_dcfetch_multi,"10010100000sssssPP001ttttt------") DEF_ENC32(Y2_dcfetchbo_nt,"10010100000sssssPP10-iiiiiiiiiii") +DEF_ENC32(V2_vallocframe_imm,"01100000100-----PP001----iiiiiii") +DEF_ENC32(V2_vallocframe_reg,"01100000100sssssPP010-----------") +DEF_ENC32(V2_vdeallocframe_imm,"01101010100-----PP001----iiiiiii") +DEF_ENC32(V2_vdeallocframe_reg,"01101001010sssssPP010-----------") +DEF_ENC32(J2_trap2,"0101010011------PP-iiiii---iii--") diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/system.idef index 9c4897a2eee..80fa0cd5618 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -48,6 +48,9 @@ Q6INSN(J2_trap1,"trap1(Rx32,#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPAC fVIRTINSN_SPSWAP(uiV,RxV); }) +Q6INSN(J2_trap2,"trap2(#u8)",ATTRIBS(A_COF,A_RESTRICT_NOPACKET), + "Trap to Operating System", { fTRAP(2,uiV); }) + Q6INSN(J2_pause,"pause(#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), "Enter low-power state for #u8 cycles",{fPAUSE(uiV);}) @@ -241,6 +244,11 @@ Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET, Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);}) Q6INSN(Y2_dcfetchbo_nt,"dcfetch(Rs32+#u11:3):nt",ATTRIBS(A_NA_NT,A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);}) + +Q6INSN(V2_vallocframe_imm,"vallocframe(#u7:0)",ATTRIBS(A_RESTRICT_NOPACKET),"Allocate vector stack frame",{ fVFRAMECHECK(VSP - (uiV << 11), VSP); }) +Q6INSN(V2_vallocframe_reg,"vallocframe(Rs32)",ATTRIBS(A_RESTRICT_NOPACKET),"Allocate vector stack frame",{ fVFRAMECHECK(VSP - (RsV << 11), VSP); }) +Q6INSN(V2_vdeallocframe_imm,"vdeallocframe(#u7:0)",ATTRIBS(A_RESTRICT_NOPACKET),"Deallocate vector stack frame",{ VSP = VSP + (uiV << 11); }) +Q6INSN(V2_vdeallocframe_reg,"vdeallocframe(Rs32)",ATTRIBS(A_RESTRICT_NOPACKET),"Deallocate vector stack frame",{ VSP = VSP + (RsV << 11); }) Q6INSN(Y4_dcfetch_multi,"dcfetch_multi(Rs32,Rt32)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_REG(RsV); fDCFETCH_MULTI(EA,fEXTRACTU_BITS(RtV,10,0));}) Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Invalidate",{fDCKILL();}) -- 2.34.1
