Add the Hexagon V79NA_1 simulator machine, with the config table of the v79 core and eight CPUs by default.
Reviewed-by: Pierrick Bouvier <[email protected]> Signed-off-by: Brian Cain <[email protected]> --- include/hw/hexagon/hexagon.h | 1 + hw/hexagon/machine_cfg_v79na_1.h.inc | 34 ++++++++++++++++++++++++++++ hw/hexagon/hexagon_dsp.c | 22 ++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 hw/hexagon/machine_cfg_v79na_1.h.inc diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index f3aee4a42e6..548135a7dd9 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -29,6 +29,7 @@ typedef enum { v73_rev = 0x8c73, v73m_rev = 0xcc73, v73nc_1_rev = 0x8b73, + v79_rev = 0x8c79, v81_rev = 0x8781, v81_sc8480xp_rev = 0x8081, v81dgb_1_rev = 0xcc81, diff --git a/hw/hexagon/machine_cfg_v79na_1.h.inc b/hw/hexagon/machine_cfg_v79na_1.h.inc new file mode 100644 index 00000000000..70a7ae58bc5 --- /dev/null +++ b/hw/hexagon/machine_cfg_v79na_1.h.inc @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v79na_1 = { + .cfgbase = 0xd8180000, + .l2tcm_size = 0x00000000, + .l2vic_base = 0xfc910000, + .l2vic_size = 0x00001000, + .csr_base = 0xfc900000, + .qtmr_region = 0xfc921000, + .cfgtable = { + .l2tcm_base = 0x0000d800, .subsystem_base = 0x00002000, + .etm_base = 0x0000d819, .l2cfg_base = 0x0000d81a, + .l1s0_base = 0x0000d900, .axi2_lowaddr = 0x00003000, + .fastl2vic_base = 0x0000d81e, .jtlb_size_entries = 0x00000080, + .coproc_present = 0x0000000d, .ext_contexts = 0x00000006, + .vtcm_base = 0x0000d900, .vtcm_size_kb = 0x00002000, + .l2tag_size = 0x00000400, .l2ecomem_size = 0x00000400, + .thread_enable_mask = 0x000000ff, .l2line_size = 0x00000080, + .l2itcm_base = 0x0000d800, .dma_version = 0x00000006, + .hvx_vec_log_length = 0x00000007, .coproc2_reg0 = 0x00000040, + .coproc2_reg1 = 0x00000020, .v2x_mode = 0x00000001, + .coproc2_reg2 = 0x00000010, .coproc2_reg3 = 0x00000020, + .coproc2_reg4 = 0x00000020, .coproc2_reg5 = 0x00000008, + .coproc2_reg6 = 0x00000016, .coproc2_reg7 = 0x00000008, + .acd_preset = 0x00000001, .mnd_preset = 0x00000001, + .l1d_size_kb = 0x00000020, .l1i_size_kb = 0x00000020, + .l1d_write_policy = 0x00000002, .vtcm_bank_width = 0x00000080, + .reserved4 = 0x00000001, .coproc2_cvt_mpy_size = 0x0000000a, + .consistency_domain = 0x000000e0, .capacity_domain = 0x00000080, + .axi3_lowaddr = 0x00004000, .coproc2_int8_subcolumns = 0x00000002, + .corecfg_present = 0x0000000d, .coproc2_fp16_acc_exp = 0x00000007, + .AXIM2_secondary_base = 0x00004000, .AXIM_data_width = 0x00000100, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index 0a2324a73b2..3854342014f 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -31,6 +31,7 @@ #include "machine_cfg_v66g_1024.h.inc" #include "machine_cfg_v68n_1024.h.inc" #include "machine_cfg_v73nc_1.h.inc" +#include "machine_cfg_v79na_1.h.inc" #include "machine_cfg_v81dgb_1.h.inc" #include "machine_cfg_v81qa_1.h.inc" #include "machine_cfg_v85na_1.h.inc" @@ -224,6 +225,22 @@ static void v81dgb_1_config_init(MachineState *machine) hexagon_common_init(machine, v81dgb_1_rev, &v81dgb_1); } +static void v79na_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v79_rev, &v79na_1); +} + +static void v79na_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Hexagon V79NA_1"; + mc->init = v79na_1_config_init; + init_mc(mc); + mc->default_cpu_type = TYPE_HEXAGON_CPU_V79; + mc->default_cpus = 8; +} + static void v81dgb_1_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -316,6 +333,11 @@ static const TypeInfo hexagon_machine_types[] = { .parent = TYPE_HEXAGON_DSP_MACHINE, .class_init = v73nc_1_init, }, + { + .name = MACHINE_TYPE_NAME("V79NA_1"), + .parent = TYPE_HEXAGON_DSP_MACHINE, + .class_init = v79na_1_init, + }, { .name = MACHINE_TYPE_NAME("V81DGB_1"), .parent = TYPE_HEXAGON_DSP_MACHINE, -- 2.34.1
