Hi Kirill, On 27/10/26 11:41, Kirill A. Korinsky wrote:
1. target/mips: make CP0 interrupt state atomic 2. target/mips: fix MIPS64 segment access checks 3. target/mips: drop hidden TLB shadowing for tlbwr 4. target/mips: add Octeon CP0 register state 5. target/mips: add Octeon CN73xx CPU model 6. target/mips: accept Octeon PageMask encodings 7. target/mips: allow Octeon unaligned accesses 8. hw/mips: add empty Octeon III machine 9. hw/mips: add Octeon CPUs and boot memory 10. hw/mips: add Octeon reset controller 11. hw/mips: add Octeon CIU3 CPU control 12. hw/mips: add Octeon CIU3 interrupt routing 13. hw/mips: add Octeon legacy CIU 14. hw/mips: add Octeon CSR window 15. hw/mips: expose Octeon reset CSRs 16. hw/mips: add Octeon MIO boot support 17. hw/mips: wire the Octeon UART 18. hw/i2c: add Octeon TWSI controller 19. hw/mips: add Octeon EMM controller 20. hw/mips: add Octeon LMC controllers 21. hw/mips: add Octeon boot support registers 22. hw/usb: add Octeon USB controller 23. hw/pci-bridge: add Octeon PCI host bridge 24. hw/pci-bridge: add Octeon PCI memory window 25. tests/functional: test Octeon III boot
All these patches miss your Signed-off-by tag: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#patch-emails-must-include-a-signed-off-by-line (You can add it automatically by replying with it to the cover.)
