On Tue, 27 Oct 2026 16:56:42 +0100, Philippe Mathieu-Daudé <[email protected]> wrote: > > On 27/10/26 11:41, Kirill A. Korinsky wrote: > > Add a CN73xx CPU definition for the Octeon III machine. The PRId, FPU > > FIR, and L2 cache geometry come from EdgeRouter Infinity ER-8-XG data; > > the remaining CP0 fields come from a Juniper SRX300 CN70xx/CN71xx dump. > > Why add the OcteonCN73XX and not a OcteonCN7[0,1]XX first? >
Because available u-boot is only for that board: https://gitlab.com/u-boot/u-boot/-/blob/main/arch/mips/dts/mrvl,cn73xx.dtsi and modern u-boot doesn't boot with non OcteonCN73XX. Here some other very old u-boot for other octeon boards: https://github.com/disdi/u-boot-cavium/tree/master but I think target this one is strange when here exists a modern one which allows to build u-boot which actually works. -- wbr, Kirill
