On 10/27/26 01:27, [email protected] wrote:
From: Alistair Francis<[email protected]>
The following changes since commit d73149283205645625bfa9fe029cfb68e4c4a9ae:
Merge tag 'samuel-thibault' ofhttps://people.debian.org/~sthibault/qemu into
staging (2026-10-24 16:09:37 +0200)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20261027
for you to fetch changes up to bf67d56f282c1ee25b67dfda3f8ca54d2bd4648e:
target/riscv: Fix CPU state access on big-endian hosts (2026-10-27 10:26:46
+1000)
----------------------------------------------------------------
RISC-V PR for 11.2
* Add experimental Zvabd extension support
* Mask vsepc according to IALIGN
* Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED
* Improve modeling of the Atlantis UART
* Fix IOMMU entry leak with ioatc-limit=0
* Fix integer handling issues in k230_gsdma and k230_decomp_gzip
* Reclaim invalidated IOATC entries for IOMMU
* Duct tape fix for QMP and RV profiles introspection
* Move RISC-V 'Z' CPU properties section to removed features
* Use TSO barriers instead of full barriers for Ztso
* Make mnstatus.MNPELP writable with Zicfilp
* Gate envcfg CBO fields on extensions
* Fix stale PMP state across reset
* Use 1ULL for a value we're going to shift by 63
* Remove unused IMISC macro
* Encode debug translation ranges in IOMMU
* Allow regular mstatus MPV/GVA writes again
* Fix uninitialised upper half in pmu_timer_trigger_irq
* Fix CPU state access on big-endian hosts
Applied, thanks.
r~
