cpu_rddsp(), exception_resume_pc(), cpu_mips_get_random(), mips_env_is_bigendian(), mo_endian_env() and sync_c0_status() only read the CPU state passed as CPUMIPSState argument, make it const.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/cpu.h | 4 ++-- target/mips/internal.h | 6 +++--- target/mips/tcg/tcg-internal.h | 2 +- target/mips/system/cp0.c | 2 +- target/mips/tcg/dsp_helper.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/system/cp0_helper.c | 2 +- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b080c5de4de8..65d302a06907 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1281,7 +1281,7 @@ struct MIPSCPUClass { }; void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); -uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); +uint32_t cpu_rddsp(uint32_t mask_num, const CPUMIPSState *env); /* * MMU modes definitions. We carefully match the indices with our @@ -1413,7 +1413,7 @@ void cpu_mips_clock_init(MIPSCPU *cpu); #endif /* !CONFIG_USER_ONLY */ /* helper.c */ -target_ulong exception_resume_pc(CPUMIPSState *env); +target_ulong exception_resume_pc(const CPUMIPSState *env); /* fpu.c */ void cpu_mips_restore_fp_status(CPUMIPSState *env); diff --git a/target/mips/internal.h b/target/mips/internal.h index 2c152e246a24..d4a4fdad9128 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -160,7 +160,7 @@ struct CPUMIPSTLBContext { } mmu; }; -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void sync_c0_status(const CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -234,12 +234,12 @@ static inline bool mips_env_is_64bit(const CPUMIPSState *env) return env->cpu_model->insn_flags & CPU_MIPS64; } -static inline bool mips_env_is_bigendian(CPUMIPSState *env) +static inline bool mips_env_is_bigendian(const CPUMIPSState *env) { return extract32(env->CP0_Config0, CP0C0_BE, 1); } -static inline MemOp mo_endian_env(CPUMIPSState *env) +static inline MemOp mo_endian_env(const CPUMIPSState *env) { return mips_env_is_bigendian(env) ? MO_BE : MO_LE; } diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 9f230e757d68..e055040b0955 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -48,7 +48,7 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def); uint32_t compute_pagemask(uint32_t val); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); +uint32_t cpu_mips_get_random(const CPUMIPSState *env); bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb); diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c index ff7d3db00c73..d946c8fdd995 100644 --- a/target/mips/system/cp0.c +++ b/target/mips/system/cp0.c @@ -24,7 +24,7 @@ #include "exec/cputlb.h" /* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +void sync_c0_status(const CPUMIPSState *env, CPUMIPSState *cpu, int tc) { int32_t tcstatus, *tcst; uint32_t v = cpu->CP0_Status; diff --git a/target/mips/tcg/dsp_helper.c b/target/mips/tcg/dsp_helper.c index 26fcfd5fb358..73934cab7786 100644 --- a/target/mips/tcg/dsp_helper.c +++ b/target/mips/tcg/dsp_helper.c @@ -3683,7 +3683,7 @@ void HELPER(wrdsp)(target_ulong rs, target_ulong mask_num, CPUMIPSState *env) cpu_wrdsp(rs, mask_num, env); } -uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env) +uint32_t cpu_rddsp(uint32_t mask_num, const CPUMIPSState *env) { uint8_t mask[6]; uint32_t ruler, i; diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 626fb00bc405..68c101a5a53a 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -27,7 +27,7 @@ #include "exec/translation-block.h" #include "accel/tcg/cpu-loop.h" -target_ulong exception_resume_pc(CPUMIPSState *env) +target_ulong exception_resume_pc(const CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c index ceffcc37323f..9c2dd1780c61 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -202,7 +202,7 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) } /* XXX: do not use a global */ -uint32_t cpu_mips_get_random(CPUMIPSState *env) +uint32_t cpu_mips_get_random(const CPUMIPSState *env) { static uint32_t seed = 1; static uint32_t prev_idx; -- 2.55.0
