On 10/28/2026 11:25 AM, Philippe Mathieu-Daudé wrote: > GDB has no knowledge of the R5900 LO1/HI1 registers and of the > upper halves of its 128-bit GPRs. Add a org.qemu.gdb.mips.r5900 > feature with lo1, hi1 and r0_hi..r31_hi, transferred as 64-bit. > > Unfortunately we need to gate on TARGET_MIPS64 because the > gpr_hi[] upper halves are only declared there. > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > configs/targets/mips64-softmmu.mak | 2 +- > configs/targets/mips64el-softmmu.mak | 2 +- > target/mips/gdbstub.c | 46 +++++++++++++++++++++++++++ > gdbstub/gdb-xml/mips64-r5900.xml | 47 ++++++++++++++++++++++++++++ > 4 files changed, 95 insertions(+), 2 deletions(-) > create mode 100644 gdbstub/gdb-xml/mips64-r5900.xml >
Reviewed-by: Pierrick Bouvier <[email protected]>
