This series adds support for AMD's upcoming EPYC Zen6 CPU models
(EPYC-Venice). The first four patches add support for the EPYC-Venice
model while patch 6/6 adds the actual model.
The EPYC-Venice model is based on the EPYC-Turin model feature set with
the following feature additions:
ERAPS, TSC Adjustment, Flush l1d, Bus Lock Detect, and Shadow Stack
and support for the following instructions:
AVX512 FP16, AVX512 IFMA, AVX NE-Convert, AVX VNNI Int8, and
AVX512 BMM instructions
as well as new cache values.
Some of these features (ERAPS, Bus Lock Detect) were only just recently
merged into the Linux kernel. It's recommended to use the latest kernel to
leverage the full support of the model.
This series also adds a new version of the EYPC-Turin model (patch 5/6)
that includes some of the features enabled as part of adding the
Venice model support. I've done this for convenience, but can split the
Turin model out into a separate series if needed. The only patches
required for the Turin support are 2/6, 3/6, and 4/6.
The Venice model had two revisions before this one, see [1]. Change log
from that is:
- Add Turin-v3 Model
- Add flush-l1d and bus-lock-detect to Venice model
- Add Bus Lock Detect DR6 support
[1]:
Link:
https://lore.kernel.org/qemu-devel/[email protected]/
Amit Shah (1):
target/i386: Add getting RAPSIZE for ERAPS enabled guests
Ben Cheatham (4):
target/i386: Update RAPSIZE definition
i386: Add Bus Lock Detect support
target/i386: Add EPYC-Turin-v3 CPU model
target/i386: Add EPYC-Venice CPU model
Nikunj A Dadhania (1):
target/i386: Add AVX512 Bit Matrix Multiply (BMM) support
target/i386/cpu.c | 163 +++++++++++++++++++++++++++++++++++++++++-
target/i386/cpu.h | 10 ++-
target/i386/kvm/kvm.c | 4 +-
3 files changed, 170 insertions(+), 7 deletions(-)
--
2.53.0
