Re: [PATCH 02/20] target/hexagon: add HLX attributes and exception cause

[Brian Cain]

On 10/29/2026 12:43 PM, Marco Liebel wrote:

Add HLX instruction attributes, a packet flag, and the
NO_COPROC3_ENABLE exception cause.

Signed-off-by: Marco Liebel <marco.lie...@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
  target/hexagon/attribs_def.h.inc | 18 ++++++++++++++++++
  target/hexagon/cpu_bits.h        |  1 +
  target/hexagon/hexswi.c          |  1 +
  target/hexagon/insn.h            |  1 +
  4 files changed, 21 insertions(+)

Reviewed-by: Brian Cain <brian.c...@oss.qualcomm.com>

diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 96ad1fd2f8..a02261ee5e 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -69,6 +69,24 @@ DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", 
"")
  /* V6 Vector attributes */
  DEF_ATTRIB(CVI, "Executes on the HVX extension", "", "")

+/* HLX attributes */

+DEF_ATTRIB(HLX, "Executes on the HLX extension", "", "")
+DEF_ATTRIB(HLX_MEM, "HLX memory instruction", "", "")
+DEF_ATTRIB(HLX_MPY, "HLX multiply instruction", "", "")
+DEF_ATTRIB(HLX_SHIFT, "HLX shift instruction", "", "")
+DEF_ATTRIB(HLX_COMMON_ALU, "HLX common ALU instruction", "", "")
+DEF_ATTRIB(HLX_PAIRED_ALU, "HLX paired ALU instruction", "", "")
+DEF_ATTRIB(HLX_ANY_RESOURCE, "HLX can use any resource", "", "")
+DEF_ATTRIB(HLX_SLOT23, "HLX can execute in slot 2 or 3", "", "")
+DEF_ATTRIB(HLX_NEW, "HLX new-value instruction", "", "")
+DEF_ATTRIB(HLX_TMP, "HLX temporary register instruction", "", "")
+DEF_ATTRIB(HLX_CU_SCALAR, "HLX scalar CU instruction", "", "")
+DEF_ATTRIB(HLX_SCALAR32, "HLX 32-bit scalar operand", "", "")
+DEF_ATTRIB(HLX_SCALAR64, "HLX 64-bit scalar operand", "", "")
+DEF_ATTRIB(HLX_LXX_MPY, "HLX Lxx multiply operation", "", "")
+DEF_ATTRIB(HLX_LXX_ADD, "HLX Lxx add operation", "", "")
+DEF_ATTRIB(NOTE_HLX_MEM, "HLX memory access notes", "", "")
+
  DEF_ATTRIB(CVI_NEW, "New value memory instruction executes on HVX", "", "")
  DEF_ATTRIB(CVI_VM, "Memory instruction executes on HVX", "", "")
  DEF_ATTRIB(CVI_VP, "Permute instruction executes on HVX", "", "")
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index c9ba09989e..65dda2175d 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -79,6 +79,7 @@ enum hex_cause {
      HEX_CAUSE_INVALID_OPCODE = 0x015, /* alias: same cause as INVALID_PACKET 
*/
      HEX_CAUSE_NO_COPROC_ENABLE = 0x016,
      HEX_CAUSE_NO_COPROC2_ENABLE = 0x018,
+    HEX_CAUSE_NO_COPROC3_ENABLE = 0x019,
      HEX_CAUSE_PRIV_USER_NO_GINSN = 0x01a,
      HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b,
      HEX_CAUSE_VECTOR_STACK_OVERFLOW = 0x01c,
diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c
index fb46c05360..f18ecaae42 100644
--- a/target/hexagon/hexswi.c
+++ b/target/hexagon/hexswi.c
@@ -923,6 +923,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs)
          case HEX_CAUSE_INVALID_OPCODE:
          case HEX_CAUSE_NO_COPROC_ENABLE:
          case HEX_CAUSE_NO_COPROC2_ENABLE:
+        case HEX_CAUSE_NO_COPROC3_ENABLE:
          case HEX_CAUSE_UNSUPPORTED_HVX_64B:
          case HEX_CAUSE_VECTOR_STACK_OVERFLOW:
          case HEX_CAUSE_REG_WRITE_CONFLICT:
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
index 5d59430da9..5751c9ced9 100644
--- a/target/hexagon/insn.h
+++ b/target/hexagon/insn.h
@@ -71,6 +71,7 @@ struct Packet {

bool pkt_has_hvx;

      Insn *vhist_insn;
+    bool pkt_has_hlx;

Insn insn[INSTRUCTIONS_MAX];

  };