From: Dongli Zhang <[email protected]> AMDVI_MMIO_EXT_FEATURES is populated from QEMU's advertised AMD-Vi extended feature set during reset. Guest writes to this register do not enable or disable any corresponding QEMU emulation behavior.
Make the register fully read-only so the visible feature bits remain controlled by QEMU. According to the AMD IOMMU SDM, bits 25:24 (DualPprLogSup), 29:28 (DualEventLogSup), and 37 (USSup) are not specified as RO. This commit modifies only bit 4 (GTSup), while leaving the rest as they are. Suggested-by: Sairaj Kodilkar <[email protected]> Signed-off-by: Dongli Zhang <[email protected]> Reviewed-by: Sairaj Kodilkar <[email protected]> Reviewed-by: Alejandro Jimenez <[email protected]> [ajz: Remove guest modification claim. AMDVI_MMIO_EXT_FEATURES writes are not handled in amdvi_mmio_write(), so a guest cannot modify the register] Signed-off-by: Alejandro Jimenez <[email protected]> --- hw/i386/amd_iommu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 00842fd487..b0a721bc00 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -244,7 +244,7 @@ (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | \ AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) -#define AMDVI_MMIO_EXT_FEATURE_RO_MASK 0xffffffffffffffefULL +#define AMDVI_MMIO_EXT_FEATURE_RO_MASK (~0ULL) /* capabilities header */ #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ -- 2.47.3
