From: Dongli Zhang <[email protected]> The MMIO read-only and write-1-to-clear masks used by amdvi_init() are currently hardcoded. The hardcoded values look ambiguous.
Define named masks for the AMD-Vi MMIO registers to make the code easier to read and understand. No functional change is intended. Suggested-by: Sairaj Kodilkar <[email protected]> Signed-off-by: Dongli Zhang <[email protected]> Reviewed-by: Sairaj Kodilkar <[email protected]> Reviewed-by: Alejandro Jimenez <[email protected]> [ajz: apply Sairaj's naming requests, update all code references] Signed-off-by: Alejandro Jimenez <[email protected]> --- hw/i386/amd_iommu.c | 18 ++++++++++-------- hw/i386/amd_iommu.h | 24 ++++++++++++++++++++---- 2 files changed, 30 insertions(+), 12 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index f52a922c69..a7f735f691 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -294,7 +294,7 @@ static void amdvi_log_event(AMDVIState *s, uint64_t *evt) /* event logging not enabled */ if (!s->evtlog_enabled || amdvi_test_mask(s, AMDVI_MMIO_STATUS, - AMDVI_MMIO_STATUS_EVT_OVF)) { + AMDVI_MMIO_STATUS_EVTLOG_OVF)) { return; } @@ -304,7 +304,8 @@ static void amdvi_log_event(AMDVIState *s, uint64_t *evt) if (evtlog_tail_next == s->evtlog_head) { /* generate overflow interrupt */ if (s->evtlog_intr) { - amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVT_OVF); + amdvi_assign_orq(s, AMDVI_MMIO_STATUS, + AMDVI_MMIO_STATUS_EVTLOG_OVF); amdvi_generate_msi_interrupt(s); } return; @@ -325,7 +326,7 @@ static void amdvi_log_event(AMDVIState *s, uint64_t *evt) amdvi_writeq_raw(s, AMDVI_MMIO_EVENT_TAIL, s->evtlog_tail); if (s->evtlog_intr) { - amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVENT_INT); + amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVTLOG_INT); amdvi_generate_msi_interrupt(s); } } @@ -1694,9 +1695,9 @@ static void amdvi_handle_control_write(AMDVIState *s) amdvi_assign_andq(s, AMDVI_MMIO_STATUS, ~AMDVI_MMIO_STATUS_CMDBUF_RUN); } if (s->evtlog_enabled) { - amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVT_RUN); + amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVTLOG_RUN); } else { - amdvi_assign_andq(s, AMDVI_MMIO_STATUS, ~AMDVI_MMIO_STATUS_EVT_RUN); + amdvi_assign_andq(s, AMDVI_MMIO_STATUS, ~AMDVI_MMIO_STATUS_EVTLOG_RUN); } trace_amdvi_control_status(control); @@ -1751,7 +1752,7 @@ static inline void amdvi_handle_evtbase_write(AMDVIState *s) { uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_BASE); - if (amdvi_readq(s, AMDVI_MMIO_STATUS) & AMDVI_MMIO_STATUS_EVENT_INT) + if (amdvi_readq(s, AMDVI_MMIO_STATUS) & AMDVI_MMIO_STATUS_EVTLOG_INT) /* Do not reset if eventlog interrupt bit is set*/ return; @@ -2572,8 +2573,9 @@ static void amdvi_init(AMDVIState *s) memset(s->mmior, 0, AMDVI_MMIO_SIZE); amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, amdvi_extended_feature_register(s), - 0xffffffffffffffef, 0); - amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); + AMDVI_MMIO_EXT_FEATURE_RO_MASK, 0); + amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, AMDVI_MMIO_STATUS_RO_MASK, + AMDVI_MMIO_STATUS_W1C_MASK); } static void amdvi_pci_realize(PCIDevice *pdev, Error **errp) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 948d8611b1..00842fd487 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -107,11 +107,25 @@ #define AMDVI_MMIO_CONTROL_INTCAPXTEN (1ULL << 51) /* MMIO status register bits */ -#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) -#define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) +#define AMDVI_MMIO_STATUS_EVTLOG_OVF (1 << 0) +#define AMDVI_MMIO_STATUS_EVTLOG_INT (1 << 1) #define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) -#define AMDVI_MMIO_STATUS_EVENT_INT (1 << 1) -#define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) +#define AMDVI_MMIO_STATUS_EVTLOG_RUN (1 << 3) +#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) +#define AMDVI_MMIO_STATUS_PPRLOG_OVF (1 << 5) +#define AMDVI_MMIO_STATUS_PPRLOG_INT (1 << 6) +#define AMDVI_MMIO_STATUS_PPRLOG_RUN (1 << 7) +#define AMDVI_MMIO_STATUS_GALOG_RUN (1 << 8) +#define AMDVI_MMIO_STATUS_GALOG_OVF (1 << 9) +#define AMDVI_MMIO_STATUS_GALOG_INT (1 << 10) + +#define AMDVI_MMIO_STATUS_RO_MASK \ + (AMDVI_MMIO_STATUS_EVTLOG_RUN | AMDVI_MMIO_STATUS_CMDBUF_RUN | \ + AMDVI_MMIO_STATUS_PPRLOG_RUN) +#define AMDVI_MMIO_STATUS_W1C_MASK \ + (AMDVI_MMIO_STATUS_EVTLOG_OVF | AMDVI_MMIO_STATUS_EVTLOG_INT | \ + AMDVI_MMIO_STATUS_COMP_INT | AMDVI_MMIO_STATUS_PPRLOG_OVF | \ + AMDVI_MMIO_STATUS_PPRLOG_INT) #define AMDVI_CMDBUF_ID_BYTE 0x07 #define AMDVI_CMDBUF_ID_RSHIFT 4 @@ -230,6 +244,8 @@ (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | \ AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) +#define AMDVI_MMIO_EXT_FEATURE_RO_MASK 0xffffffffffffffefULL + /* capabilities header */ #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ -- 2.47.3
