On 3/11/26 18:26, Peter Maydell wrote:
We previously allowed the GICv5 on any 64-bit CPU, with a hack where
enabling the GICv5 silently disabled AArch32 for EL1..3.
Now that we have a separate 'max-v8' and 'max-v9' where max-v9
correctly doesn't implement AArch32 at EL1..3, we can fix the "when
do we expose the has_gcie property" condition so that we only allow
the GICv5 when AArch32 doesn't exist above EL0, and remove the hack
disabling AArch32.
We could instead have defined a new ARM_FEATURE_V9, but "allow the
feature to be present on CPUs where it doesn't actively break
anything" fits the way we've generally handled things in QEMU, and it
avoids having a new V9 feature bit that we only use for this one
thing and where it's not clear when we should be setting it for KVM,
hvf, etc accelerators.
In practice the only CPUs which will allow GICv5 now are max, max-v9
and a64fx.
Signed-off-by: Peter Maydell <[email protected]>
---
target/arm/cpu-features.h | 8 ++++++++
target/arm/cpu.c | 37 +++++++------------------------------
2 files changed, 15 insertions(+), 30 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
