> > The latter depends how general you want the solution to be. One > > possibility is for the device DMA+registration routines map everything > > onto CPU address space. > > Interesting idea, do you mean that all individual bus address spaces > could exist in system view in the same large address space outside the > target CPU address space? Then some of the translations could become > simple offset operations.
No, I was basically assuming that all cpu->device mappings are linear offsets. This means you need almost no changes to the current CPU access code. You can also arrange for all device DMA requests to be translated into CPU physical addresses (VIA IOMMU, or whatever), then treat them the same as if they were CPU accesses. However on second thoughts this probably isn't such a clever idea. There are some potentially interesting cases it can't handle. I'll see if I can come up with an actual proposal. My current theory is that we should be able to combine the bus mappings with the TLB fill, which should help mitigate the overhead. Paul