Il 24/05/2013 07:49, peter.crosthwa...@xilinx.com ha scritto:
> +static const MemoryRegionOps devcfg_reg_ops = {
> + .read = register_read_memory_le,
> + .write = register_write_memory_le,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
What happens if you have registers of mixed size within the same "bank"?
> + }
> +};
> +
> +static void xilinx_devcfg_realize(DeviceState *dev, Error **errp)
> +{
> + XilinxDevcfg *s = XILINX_DEVCFG(dev);
> + const char *prefix = object_get_canonical_path(OBJECT(dev));
> + int i;
> +
> + for (i = 0; i < R_MAX; ++i) {
> + RegisterInfo *r = &s->regs_info[i];
> +
> + *r = (RegisterInfo) {
> + .data = &s->regs[i],
> + .data_size = sizeof(uint32_t),
> + .access = &xilinx_devcfg_regs_info[i],
> + .debug = XILINX_DEVCFG_ERR_DEBUG,
> + .prefix = prefix,
> + .opaque = s,
> + };
> + memory_region_init_io(&r->mem, &devcfg_reg_ops, r, "devcfg-regs", 4);
Could you add a register_init function that does register_reset +
memory_region_init_io?
> + memory_region_add_subregion(&s->iomem, i * 4, &r->mem);
Paolo
