On Fri, May 24, 2013 at 03:47:33PM +1000, peter.crosthwa...@xilinx.com wrote: > From: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > > This API provides some encapsulation of registers and factors our some > common functionality to common code. Bits of device state (usually MMIO > registers), often have all sorts of access restrictions and semantics > associated with them. This API allow you to define what those > restrictions are on a bit-by-bit basis. > > Helper functions are then used to access the register which observe the > semantics defined by the RegisterAccessInfo struct. > > Some features: > Bits can be marked as read_only (ro field) > Bits can be marked as write-1-clear (w1c field) > Reset values can be defined (reset) > Bits can throw guest errors when written certain values (ge0, ge1) > Bits can throw unimp errors when written certain values (ui0, ui1) > Bits can be marked clear on read (cor) > Pre and post action callbacks can be added to read and write ops > Verbose debugging info can be enabled/disabled > > Useful for defining device register spaces in a data driven way. Cuts > down on a lot of the verbosity and repetition in the switch-case blocks > in the standard foo_mmio_read/write functions. > > Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@gmail.com> > --- > changed from v2: > Simplified! Removed pre-read, nwx, wo > Removed byte loops (Gerd Review) > Made data pointer optional > Added fast paths for simple registers > Moved into hw/core and include/hw (Paolo Review) > changed from v1: > Rebranded as the "Register API" - I think thats probably what it is. > Near total rewrite of implementation. > De-arrayified reset (this is client/Memory APIs job). > Moved out of bitops into its own file (Blue review) > Added debug, the register pointer, and prefix to a struct (Blue Review) > Made 64-bit to play friendlier with memory API (Blue review) > Made backend storage uint8_t (MST review) > Added read/write callbacks (Blue review) > Added ui0, ui1 (Blue review) > Moved re-purposed width (now byte width defining actual storage size) > Arrayified ge0, ge1 (ui0, ui1 too) and added .reason > Added wo field (not an April fools joke - this has genuine meaning here) > Added we mask to write accessor > > hw/core/Makefile.objs | 1 + > hw/core/register.c | 190 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > include/hw/register.h | 129 ++++++++++++++++++++++++++++++++++ > 3 files changed, 320 insertions(+) > create mode 100644 hw/core/register.c > create mode 100644 include/hw/register.h > > diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs > index 950146c..210cb1a 100644 > --- a/hw/core/Makefile.objs > +++ b/hw/core/Makefile.objs > @@ -2,6 +2,7 @@ > common-obj-y += qdev.o qdev-properties.o > # irq.o needed for qdev GPIO handling: > common-obj-y += irq.o > +common-obj-y += register.o > > common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o > common-obj-$(CONFIG_XILINX_AXI) += stream.o > diff --git a/hw/core/register.c b/hw/core/register.c > new file mode 100644 > index 0000000..b10212e > --- /dev/null > +++ b/hw/core/register.c > @@ -0,0 +1,190 @@ > +/* > + * Register Definition API > + * > + * Copyright (c) 2013 Xilinx Inc. > + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwa...@xilinx.com> > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See > + * the COPYING file in the top-level directory. > + */ > + > +#include "hw/register.h" > +#include "qemu/log.h" > + > +static inline void register_write_log(RegisterInfo *reg, int dir, uint64_t > val, > + int mask, const char *msg, > + const char *reason) > +{ > + qemu_log_mask(mask, "%s:%s bits %#" PRIx64 " %s write of %d%s%s\n", > + reg->prefix, reg->access->name, val, msg, dir, > + reason ? ": " : "", reason ? reason : ""); > +} > + > +static inline void register_write_val(RegisterInfo *reg, uint64_t val) > +{ > + if (!reg->data) { > + return; > + } > + switch (reg->data_size) { > + case 1: > + *(uint8_t *)reg->data = val; > + break; > + case 2: > + *(uint16_t *)reg->data = val; > + break; > + case 4: > + *(uint32_t *)reg->data = val; > + break; > + case 8: > + *(uint64_t *)reg->data = val; > + break; > + default: > + abort(); > + } > +} > + > +static inline uint64_t register_read_val(RegisterInfo *reg) > +{ > + switch (reg->data_size) { > + case 1: > + return *(uint8_t *)reg->data; > + case 2: > + return *(uint16_t *)reg->data; > + case 4: > + return *(uint32_t *)reg->data; > + case 8: > + return *(uint64_t *)reg->data; > + default: > + abort(); > + } > + return 0; /* unreachable */ > +} > + > +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we) > +{ > + uint64_t old_val, new_val, test, no_w_mask; > + const RegisterAccessInfo *ac; > + const RegisterAccessError *rae; > + > + assert(reg); > + > + ac = reg->access; > + if (reg->write_lite && !~we) { /* fast path!! */ > + new_val = val; > + goto register_write_fast; > + } > + > + if (!ac || !ac->name) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state " > + "(written value: %#" PRIx64 ")\n", reg->prefix, val); > + return; > + } > + > + no_w_mask = ac->ro | ac->w1c | ~we; > + > + if (reg->debug) { > + qemu_log("%s:%s: write of value %#" PRIx64 "\n", reg->prefix, > ac->name, > + val); > + } > + > + if (qemu_loglevel_mask(LOG_GUEST_ERROR)) { > + for (rae = ac->ge1; rae && rae->mask; rae++) { > + test = val & rae->mask; > + if (test) { > + register_write_log(reg, 1, test, LOG_GUEST_ERROR, > + "invalid", rae->reason); > + } > + } > + for (rae = ac->ge0; rae && rae->mask; rae++) { > + test = ~val & rae->mask; > + if (test) { > + register_write_log(reg, 0, test, LOG_GUEST_ERROR, > + "invalid", rae->reason); > + } > + } > + } > + > + if (qemu_loglevel_mask(LOG_UNIMP)) { > + for (rae = ac->ui1; rae && rae->mask; rae++) { > + test = val & rae->mask; > + if (test) { > + register_write_log(reg, 1, test, LOG_GUEST_ERROR, > + "unimplmented", rae->reason); > + } > + } > + for (rae = ac->ui0; rae && rae->mask; rae++) { > + test = ~val & rae->mask; > + if (test) { > + register_write_log(reg, 0, test, LOG_GUEST_ERROR, > + "unimplemented", rae->reason); > + } > + } > + } > + > + old_val = reg->data ? register_read_val(reg) : ac->reset; > + > + new_val = (val & ~no_w_mask) | (old_val & no_w_mask); > + new_val &= ~(val & ac->w1c); > + > + if (ac->pre_write) { > + new_val = ac->pre_write(reg, new_val); > + } > +register_write_fast: > + register_write_val(reg, new_val); > + if (ac->post_write) { > + ac->post_write(reg, new_val); > + } > +} > + > +uint64_t register_read(RegisterInfo *reg) > +{ > + uint64_t ret; > + const RegisterAccessInfo *ac; > + > + assert(reg); > + > + ac = reg->access; > + if (!ac || !ac->name) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device > state\n", > + reg->prefix); > + return 0; > + } > + > + ret = reg->data ? register_read_val(reg) : ac->reset; > + > + if (!reg->read_lite) { > + register_write_val(reg, ret & ~ac->cor); > + if (reg->debug) { > + qemu_log("%s:%s: read of value %#" PRIx64 "\n", reg->prefix, > + ac->name, ret); > + } > + } > + > + if (ac->post_read) { > + ret = ac->post_read(reg, ret); > + } > + > + return ret; > +} > + > +void register_reset(RegisterInfo *reg) > +{ > + assert(reg); > + const RegisterAccessInfo *ac; > + > + if (!reg->data || !reg->access) { > + return; > + } > + > + ac = reg->access; > + > + /* if there are no debug msgs and no RMW requirement, mark for fast > write */ > + reg->write_lite = reg->debug || ac->ro || ac->w1c || ac->pre_write || > + ((ac->ge0 || ac->ge1) && qemu_loglevel_mask(LOG_GUEST_ERROR)) || > + ((ac->ui0 || ac->ui1) && qemu_loglevel_mask(LOG_UNIMP)) > + ? false : true; > + /* no debug and no clear-on-read is a fast read */ > + reg->read_lite = reg->debug || ac->cor ? false : true; > + > + register_write_val(reg, reg->access->reset); > +} > diff --git a/include/hw/register.h b/include/hw/register.h > new file mode 100644 > index 0000000..a4a8319 > --- /dev/null > +++ b/include/hw/register.h > @@ -0,0 +1,129 @@ > +/* > + * Register Definition API > + * > + * Copyright (c) 2013 Xilinx Inc. > + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwa...@xilinx.com> > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See > + * the COPYING file in the top-level directory. > + */ > + > +#ifndef REGISTER_H > +#define REGISTER_H > + > +#include "exec/memory.h" > + > +typedef struct RegisterInfo RegisterInfo; > +typedef struct RegisterAccessInfo RegisterAccessInfo; > + > +/** > + * A register access error message > + * @mask: Bits in the register the error applies to > + * @reason: Reason why this access is an error > + */ > + > +typedef struct RegisterAccessError { > + uint64_t mask; > + const char *reason; > +} RegisterAccessError; > + > +/** > + * Access description for a register that is part of guest accessible device > + * state. > + * > + * @name: String name of the register > + * @ro: whether or not the bit is read-only > + * @w1c: bits with the common write 1 to clear semantic. > + * @reset: reset value. > + * @cor: Bits that are clear on read > + * > + * @ge1: Bits that when written 1 indicate a guest error > + * @ge0: Bits that when written 0 indicate a guest error > + * @ui1: Bits that when written 1 indicate use of an unimplemented feature > + * @ui0: Bits that when written 0 indicate use of an unimplemented feature > + * > + * @pre_write: Pre write callback. Passed the value that's to be written, > + * immediately before the actual write. The returned value is what is > written, > + * giving the handler a chance to modify the written value. > + * @post_write: Post write callback. Passed the written value. Most write > side > + * effects should be implemented here. > + * > + * @post_read: Post read callback. Passes the value that is about to be > returned > + * for a read. The return value from this function is what is ultimately > read, > + * allowing this function to modify the value before return to the client. > + */ > + > +struct RegisterAccessInfo { > + const char *name; > + uint64_t ro; > + uint64_t w1c; > + uint64_t reset; > + uint64_t cor; > + > + const RegisterAccessError *ge0; > + const RegisterAccessError *ge1; > + const RegisterAccessError *ui0; > + const RegisterAccessError *ui1; > + > + uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val); > + void (*post_write)(RegisterInfo *reg, uint64_t val); > + > + uint64_t (*post_read)(RegisterInfo *reg, uint64_t val); > +}; > + > +/** > + * A register that is part of guest accessible state > + * @data: pointer to the register data. Will be cast > + * to the relevant uint type depending on data_size. > + * @data_size: Size of the register in bytes. Must be > + * 1, 2, 4 or 8 > + * @data_big_endian: Define endianess of data register > + * > + * @access: Access desciption of this register > + * > + * @debug: Whether or not verbose debug is enabled > + * @prefix: String prefix for log and debug messages > + * > + * @opaque: Opaque data for the register > + */ > + > +struct RegisterInfo { > + void *data; > + int data_size; > + > + const RegisterAccessInfo *access; > + > + bool debug; > + const char *prefix; > + > + void *opaque; > + /* private */ > + bool read_lite; > + bool write_lite; > +}; > + > +/** > + * write a value to a register, subject to its restrictions > + * @reg: register to write to > + * @val: value to write > + * @we: write enable mask > + */ > + > +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we); > + > +/** > + * read a value from a register, subject to its restrictions > + * @reg: register to read from > + * returns: value read > + */ > + > +uint64_t register_read(RegisterInfo *reg); > + > +/** > + * reset a register > + * @reg: register to reset > + */ > + > +void register_reset(RegisterInfo *reg); > + > +#endif > -- > 1.8.3.rc1.44.gb387c77.dirty >