From: Paul Burton <paul.bur...@imgtec.com>
The firmware commonly used with MIPS Malta boards (YAMON) reads the
status of the pflash with a 32bit memory access. On real hardware
this results in the status byte being mirrored in the upper 16 bits
of the read value. For example if the status byte is represented by
SS then the hardware reads 0x00SS00SS. The YAMON firmware compares the
status against 32bit values expecting the mirrored value and fails
without it.
Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Signed-off-by: Leon Alrae <leon.al...@imgtec.com>
---
hw/block/pflash_cfi01.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 63d7c99..047ee65 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -186,6 +186,9 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
case 0xe8: /* Write block */
/* Status register read */
ret = pfl->status;
+ if (width > 2) {
+ ret |= pfl->status << 16;
+ }
DPRINTF("%s: status %x\n", __func__, ret);
break;
case 0x90:
--
1.7.5.4
