SCR.{IRQ/FIQ} bits allows to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <s.fedo...@samsung.com>
---
target-arm/helper.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ba442c0..6472c09 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2620,12 +2620,19 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.c1_scr & (1 << 1)) {
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.c1_scr & (1 << 2)) {
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC:
--
1.7.9.5
