On 20 December 2013 14:12, Fedorov Sergey <s.fedo...@samsung.com> wrote: > I've briefly looked at the v8 ARM ARM. As I can see there is no banked > system control registers in AArch64. Seems the concept is changed to provide > separate registers for each meaningful execution level. Please, correct me > if I am wrong.
Yes, I think this is generally correct. > So I think there shouldn't be "active" and "banked" fields for banked > AArch32 CP15 registers as in my patch. Seems it is worth to use AArch64 view > of system control registers as a basis. That means there would be separate S > and NS register fields in CPU state structure that will me mapped to > separate AArch64 registers. ARMCPRegInfo structure would have additional > field holding NS register state filed offset for AArch32 banked registers. This sounds like it could work, though there are some wrinkles for registers with readfns/writefns -- do we have extra s vs ns read/write functions, or just one set of functions which has to look in env->ns to figure out whether to use the S or NS version? > Which branch in https://git.linaro.org/people/peter.maydell/qemu-arm.git > repository holds the most actual A64 support? It's still a work in progress so it depends what you want. a64-third-fourth-set is the last set of patches that went out for review, and should generally work for integer instructions. a64-working is my work-in-progress branch so it will have the most recent versions of everything, but it rebases frequently and is liable to occasionally be broken... thanks -- PMM