On 23 December 2013 07:43, Fedorov Sergey <s.fedo...@samsung.com> wrote: > > On 12/20/2013 06:33 PM, Peter Maydell wrote: >> This sounds like it could work, though there are some wrinkles for >> registers with readfns/writefns -- do we have extra s vs ns read/write >> functions, or just one set of functions which has to look in env->ns to >> figure out whether to use the S or NS version? > > What about defining a separate ARMCPRegInfo for each banked AArch32 > system register? I think it would be close to AArch64 concept. It would > allow to use separate read/write handlers if necessary or reuse the same > handlers otherwise. When the handlers is not used, the translation code > would simply lookup the ARMCPRegInfo for corresponding secure state and > use the field offset.
Yes, I was thinking about that the other day -- add the S/NS to the set of things in the hash table key, and have the 32 bit MCR/MRC code pass in the right value to get the correct banked register out. (We'd have to make all the non-banked registers go into the hashtable twice, though, but that's not a big deal I think.) thanks -- PMM