On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote: > This adds DABRX SPR. > > As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not > have them (as it implements more powerful facility instead), this limits > DABR/DABRX registration by POWER7 (inclusive). > > Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru> > --- > target-ppc/translate_init.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 237074d..2c076b0 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_DABR, 0x00000000); > + > + spr_register_kvm(env, SPR_DABRX, "DABRX", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + KVM_REG_PPC_DABRX, 0x00000000); > } >
Is no read nor write access in any mode what you intended? It appears to be supervisor read/write in the 970 UM. > static void gen_spr_970_dbg(CPUPPCState *env) > @@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int > version) > gen_spr_book3s_altivec(env); > gen_spr_book3s_pmu_hypv(env); > gen_spr_book3s_pmu_user(env); > - gen_spr_book3s_dbg(env); > gen_spr_book3s_common(env); > > switch (version) { > @@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int > version) > gen_spr_power8_pmu_user(env); > gen_spr_power8_tm(env); > } > + if (version < BOOK3S_CPU_POWER8) { > + gen_spr_book3s_dbg(env); > + } > #if !defined(CONFIG_USER_ONLY) > switch (version) { > case BOOK3S_CPU_970: >