On 06/04/2014 02:51 AM, Greg Kurz wrote: > On Tue, 3 Jun 2014 19:28:04 +1000 > Alexey Kardashevskiy <a...@ozlabs.ru> wrote: > >> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from >> the H_SET_MODE, for POWER8 (PowerISA 2.07) only. >> >> This defines AIL flags for LPCR special register. >> >> This changes @excp_prefix according to the mode, takes effect in TCG. >> >> This turns support of a new capability PPC2_ISA207S flag for TCG. >> >> Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru> >> --- >> hw/ppc/spapr_hcall.c | 47 >> +++++++++++++++++++++++++++++++++++++++++++++++ >> include/hw/ppc/spapr.h | 5 +++++ >> target-ppc/cpu.h | 4 +++- >> target-ppc/excp_helper.c | 7 +++++-- >> 4 files changed, 60 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c >> index cff3b0f..a2941f4 100644 >> --- a/hw/ppc/spapr_hcall.c >> +++ b/hw/ppc/spapr_hcall.c >> @@ -743,6 +743,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU >> *cpu, >> return H_UNSUPPORTED_FLAG; >> } >> >> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu, >> + target_ulong mflags, >> + target_ulong value1, >> + target_ulong value2) >> +{ >> + CPUState *cs; >> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); >> + target_ulong prefix; >> + >> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) { >> + return H_P2; >> + } >> + if (value1) { >> + return H_P3; >> + } >> + if (value2) { >> + return H_P4; >> + } >> + >> + switch (mflags) { >> + case H_SET_MODE_ADDR_TRANS_NONE: >> + prefix = 0; >> + break; >> + case H_SET_MODE_ADDR_TRANS_0001_8000: >> + prefix = 0x18000; >> + break; >> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000: >> + prefix = 0xC000000000004000; >> + break; >> + default: >> + return H_UNSUPPORTED_FLAG; >> + } >> + >> + CPU_FOREACH(cs) { >> + CPUPPCState *env = &POWERPC_CPU(cpu)->env; >> + >> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL); >> + env->excp_prefix = prefix; >> + } >> + >> + return H_SUCCESS; >> +} >> + >> static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, >> target_ulong opcode, target_ulong *args) >> { >> @@ -753,6 +796,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, >> sPAPREnvironment *spapr, >> case H_SET_MODE_RESOURCE_LE: >> ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]); >> break; >> + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: >> + ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0], >> + args[2], args[3]); >> + break; >> } >> >> return ret; >> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h >> index 4ffb903..08c301f 100644 >> --- a/include/hw/ppc/spapr.h >> +++ b/include/hw/ppc/spapr.h >> @@ -164,6 +164,11 @@ typedef struct sPAPREnvironment { >> #define H_SET_MODE_ENDIAN_BIG 0 >> #define H_SET_MODE_ENDIAN_LITTLE 1 >> >> +/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ >> +#define H_SET_MODE_ADDR_TRANS_NONE 0 >> +#define H_SET_MODE_ADDR_TRANS_0001_8000 2 >> +#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 >> + >> /* VASI States */ >> #define H_VASI_INVALID 0 >> #define H_VASI_ENABLED 1 >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h >> index e33828a..4a8e0c4 100644 >> --- a/target-ppc/cpu.h >> +++ b/target-ppc/cpu.h >> @@ -467,6 +467,8 @@ struct ppc_slb_t { >> #define MSR_LE 0 /* Little-endian mode 1 >> hflags */ >> >> #define LPCR_ILE (1 << (63-38)) >> +#define LPCR_AIL 0x01800000 /* Alternate interrupt location */ >> +#define LPCR_AIL_SH (63-40) >> > > You seem to have missed (or disgarded) a comment on your previous post > about magic numbers. Also FWIW most of the bit shifts in this file have > the _SHIFT suffix in their name:
I simply forgot it :( Thanks for the reminder, v5 is coming. > #define LPCR_AIL_SHIFT (63-40) > #define LPCR_AIL (3 << LPCR_AIL_SHIFT) > >> #define msr_sf ((env->msr >> MSR_SF) & 1) >> #define msr_isf ((env->msr >> MSR_ISF) & 1) >> @@ -2009,7 +2011,7 @@ enum { >> PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ >> PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ >> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ >> - PPC2_ALTIVEC_207) >> + PPC2_ALTIVEC_207 | PPC2_ISA207S) >> }; >> >> >> /*****************************************************************************/ >> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c >> index fd89d99..b39bf1b 100644 >> --- a/target-ppc/excp_helper.c >> +++ b/target-ppc/excp_helper.c >> @@ -619,8 +619,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int >> excp_model, int excp) >> if (asrr1 != -1) { >> env->spr[asrr1] = env->spr[srr1]; >> } >> - /* If we disactivated any translation, flush TLBs */ >> - if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { >> + >> + if (env->spr[SPR_LPCR] & LPCR_AIL) { >> + new_msr |= (1 << MSR_IR) | (1 << MSR_DR); >> + } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { >> + /* If we disactivated any translation, flush TLBs */ >> tlb_flush(cs, 1); >> } >> > > > -- Alexey