In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target-arm/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f964df..4c9e237 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8997,7 +8997,8 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
}
if (size == 3) {
- for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
+ assert(is_q);
+ for (pass = 0; pass < 2; pass++) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
--
1.8.5.4
