The maximum block size for AArch64 address translation is 2GB. This means
that we need a ULL suffix on our shift to avoid shifting into the sign
bit of a signed 32 bit integer.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ec031f5..cbad223 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3926,7 +3926,7 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
* These are basically the same thing, although the number
* of bits we pull in from the vaddr varies.
*/
- page_size = (1 << ((granule_sz * (4 - level)) + 3));
+ page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor and merge with table attrs */
if (arm_feature(env, ARM_FEATURE_V8)) {
--
1.8.5.4
