When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler <aggel...@ethz.ch> --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 25 ++++++++++++++----------- 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7f5124c..048ede9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -299,7 +299,15 @@ typedef struct CPUARMState { }; }; uint64_t far_el3; - uint64_t par_el1; /* Translation result. */ + struct { /* Translation result. */ + union { + uint64_t par_ns; + uint64_t par_s; + }; + union { + uint64_t par_el1; + }; + }; uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c9_pmcr; /* performance monitor control register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 47bf7a7..c3195bd 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1281,7 +1281,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * fault. */ } - env->cp15.par_el1 = par64; + A32_BANKED_CURRENT_REG_SET(env, par, par64); } else { /* ret is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). @@ -1291,14 +1291,16 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* We do not set any attribute bits in the PAR */ if (page_size == (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; + A32_BANKED_CURRENT_REG_SET(env, par, + (phys_addr & 0xff000000) | 1 << 1); } else { - env->cp15.par_el1 = phys_addr & 0xfffff000; + A32_BANKED_CURRENT_REG_SET(env, par, phys_addr & 0xfffff000); } } else { - env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | - ((ret & (1 << 12)) >> 6) | - ((ret & 0xf) << 1) | 1; + A32_BANKED_CURRENT_REG_SET(env, par, + ((ret & (1 << 10)) >> 5) | + ((ret & (1 << 12)) >> 6) | + ((ret & 0xf) << 1) | 1); } } } @@ -1306,9 +1308,9 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static const ARMCPRegInfo vapa_cp_reginfo[] = { { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), - .writefn = par_write }, + .access = PL1_RW, .resetvalue = 0, .writefn = par_write, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) } }, #ifndef CONFIG_USER_ONLY { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, @@ -1755,8 +1757,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, - .access = PL1_RW, .type = ARM_CP_64BIT, - .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, + .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), -- 1.8.3.2