Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
---
target-arm/cpu.h | 3 ++
target-arm/helper.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 140 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b786a5a..52e679f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -768,6 +768,9 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
+inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode,
+ uint32_t excp_idx, uint32_t cur_el,
+ bool secure);
/* Interface between CPU and Interrupt controller. */
void armv7m_nvic_set_pending(void *opaque, int irq);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5822353..8333b52 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3224,6 +3224,21 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env,
uint32_t mode)
return 0;
}
+inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode,
+ uint32_t excp_idx, uint32_t cur_el,
+ bool secure)
+{
+ switch (excp_idx) {
+ case EXCP_IRQ:
+ *target_mode = ARM_CPU_MODE_IRQ;
+ break;
+ case EXCP_FIQ:
+ *target_mode = ARM_CPU_MODE_FIQ;
+ break;
+ }
+ return 1;
+}
+
unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
{
return 1;
@@ -3285,6 +3300,128 @@ void switch_mode(CPUARMState *env, int mode)
}
/*
+ * Determine the target EL for physical exceptions
+ */
+inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode,
+ uint32_t excp_idx, uint32_t cur_el,
+ bool secure)
+{
+ CPUARMState *env = cs->env_ptr;
+ uint32_t target_el = 1;
+ uint32_t excp_mode = 0;
+
+ bool scr_routing = 0; /* IRQ, FIQ, EA */
+ bool hcr_routing = 0; /* IMO, FMO, AMO */
+
+ switch (excp_idx) {
+ case EXCP_IRQ:
+ scr_routing = (env->cp15.scr_el3 & SCR_IRQ);
+ hcr_routing = (env->cp15.hcr_el2 & HCR_IMO);
+ excp_mode = ARM_CPU_MODE_IRQ;
+ break;
+ case EXCP_FIQ:
+ scr_routing = (env->cp15.scr_el3 & SCR_FIQ);
+ hcr_routing = (env->cp15.hcr_el2 & HCR_FMO);
+ excp_mode = ARM_CPU_MODE_FIQ;
+ }
+
+ /* If HCR.TGE is set all exceptions that would be routed to EL1 are
+ * routed to EL2 (in non-secure world).
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2) && (env->cp15.hcr_el2 & HCR_TGE)) {
+ hcr_routing = 1;
+ }
+
+ /* Determine target EL according to ARM ARMv8 tables G1-15 and G1-16 */
+ if (arm_el_is_aa64(env, 3)) {
+ /* EL3 in Aarch64 */
+ if (scr_routing) {
+ /* IRQ|FIQ|EA == 1 */
+ target_el = 3;
+ } else {
+ if (hcr_routing) {
+ /* IRQ|FIQ|EA == 0
+ * IMO|FMO|AMO == 1 */
+ if (secure) {
+ /* Secure */
+ target_el = 1;
+ if (!arm_el_is_aa64(env, 1)) {
+ /* EL1 using Aarch32 */
+ *target_mode = ARM_CPU_MODE_ABT;
+ }
+ } else if (cur_el < 2) {
+ /* Non-Secure goes to EL2 */
+ target_el = 2;
+ if (!arm_el_is_aa64(env, 2)) {
+ /* EL2 using Aarch32 */
+ *target_mode = ARM_CPU_MODE_HYP;
+ }
+ }
+ } else if (env->cp15.scr_el3 & SCR_RW) {
+ /* IRQ|FIQ|EA == 0
+ * IMO|FMO|AMO == 0
+ * RW == 1 (Next lower level is Aarch64)
+ */
+ if (cur_el < 2) {
+ target_el = 1;
+ } else {
+ /* Interrupt not taken but remains pending */
+ }
+ } else {
+ /* IRQ|FIQ|EA == 0
+ * IMO|FMO|AMO == 0
+ * RW == 0 (Next lower level is Aarch64)
+ */
+ if (cur_el < 2) {
+ target_el = 1;
+ *target_mode = ARM_CPU_MODE_ABT;
+ } else if (cur_el == 2) {
+ target_el = 2;
+ *target_mode = ARM_CPU_MODE_HYP;
+ } else {
+ /* Interrupt not taken but remains pending */
+ }
+ }
+ }
+ } else {
+ /* EL3 in Aarch32 */
+ if (scr_routing) {
+ /* IRQ|FIQ|EA == 1 */
+ target_el = 3;
+ *target_mode = ARM_CPU_MODE_MON;
+ } else {
+ if (hcr_routing) {
+ /* IRQ|FIQ|EA == 0
+ * IMO|FMO|AMO == 1
+ */
+ if (secure) {
+ target_el = 3;
+ *target_mode = excp_mode;
+ } else {
+ target_el = 2;
+ *target_mode = ARM_CPU_MODE_HYP;
+ }
+ } else {
+ /* IRQ|FIQ|EA == 0
+ * IMO|FMO|AMO == 0
+ */
+ if (cur_el < 2) {
+ target_el = 1;
+ *target_mode = excp_mode;
+ } else if (cur_el == 2) {
+ target_el = 2;
+ *target_mode = ARM_CPU_MODE_HYP;
+ } else if (secure) {
+ target_el = 3;
+ *target_mode = excp_mode;
+ }
+ }
+ }
+ }
+ return target_el;
+}
+
+/*
* Determine the target EL for a given exception type.
*/
unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
--
1.8.3.2
