On Wed, Sep 10, 2014 at 9:39 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Tue, Sep 9, 2014 at 11:59 PM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 9 September 2014 14:35, Peter Crosthwaite >> <peter.crosthwa...@xilinx.com> wrote: >>> Does ARMv7M actually mandate the existence of RAM and flash like this >>> at all? >> >> No. It does have a well defined address map that pretty >> strongly suggests that you ought to have flash and RAM >> at certain addresses, but the flash and RAM are not part >> of the CPU core itself. >> >> (Bitbanding, on the other hand, is part of the CPU core >> and the memory region setup for it should stay in this >> function.) >> >>> Given the complex setup of STM (with the memory aliases etc) >>> I'm now of the belief that all RAM and FLASH init should be handled by >>> the SoC level. >> >> Agreed. > > That makes everything so much easier. I was stuck at how to do the > memory aliasing. > I will move the memory region inits out of the function and put them into > the SoC level. >
Sounds ok to me. Regards, Peter > Is everyone happy enough with then using the armv7_init function as I > have in this > patch (except with out the Flash and SRAM parts)? So both Stellaris > and STM32F205 > call the function. The only change from the current implementation > would be the number > of interrupt lines, which would become a parameter. > > Thanks, > > Alistair > >> >> -- PMM >
