Hi everybody, Here is the plan we will follow:
We will be focusing - from the outset - on the end goal of multi-threaded TCG in full system emulation mode. On the way, we expect this will ‘fix’ user mode. The plan is: * Create one cache per CPU as a first step. We can do more next and share a cache. * Update tb_* to add a pointer to their cache. * Add atomic instruction support to the TGC (first on ARM). * Make tb_invalidate work between all cache. * Modify main-loop for multi-thread. * Memory access (eg: for device) are not thread safe that need to be fixed. Initial plan simply globally mutex memory accesses - this may be optimised later. * For now, irq handler for CPU seems ok but we need to check. We will discuss this during the call tomorrow. Thanks, Fred
