On 6 May 2015 at 23:50, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote: > Add the ARM cortex A53 processor definition. Similar to A57, but with > different L1 I cache policy, phys addr size and different cache > geometries. The cache sizes is implementation configurable, but use > these values (from Xilinx Zynq MPSoC) as a default until cache size > configurability is added. > > Acked-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > ---
It would be nice if you could get the CPU name right in the commit message: it's "Cortex-A53" (caps, hyphen). Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
