On 28 May 2015 at 06:30, Edgar E. Iglesias <edgar.igles...@xilinx.com> wrote: > On Tue, May 19, 2015 at 07:33:23PM +0100, Peter Maydell wrote: >> If the SCTLR.UMA trap bit is set then attempts by EL0 to update >> the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" >> instructions will raise an exception. We were failing to set >> the syndrome information for this exception, which meant that >> it would be reported as a repeat of whatever the previous >> exception was. Set the correct syndrome information. >> --- >> target-arm/op_helper.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c >> index 43e3457..5af4a0e 100644 >> --- a/target-arm/op_helper.c >> +++ b/target-arm/op_helper.c >> @@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, >> uint32_t imm) >> */ >> if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { >> env->exception.target_el = exception_target_el(env); >> + env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, >> 3), >> + extract32(op, 3, 3), >> 4, >> + 0x1f, imm, 0); > > Did you possibly reverse the argument order of 0x1f and imm?
Ah, you're right; I was confused because the argument order of our syn_aa64_sysregtrap() and the pseudocode AArch64.SystemRegisterTrap is different (the latter follows the field order in the syndrome register and ours doesn't). -- PMM